In an embodiment, a semiconductor device includes a High Electron Mobility Transistor (HEMT) including a floating gate. The floating gate includes two or more electrically separated floating gate segments.

A semiconductor memory device is provided. The semiconductor memory device includes a semiconductor substrate and transistor structures. The transistor structures are disposed on the semiconductor substrate. Each of the transistor structures includes a semiconductor layer, a floating gate, a control gate, a tunneling oxide layer, and an inter-gate dielectric layer. The semiconductor substrate and the semiconductor layer have the same conductivity type and different doping concentrations. The floating gate covers a sidewall of the semiconductor layer and has a curved sidewall opposite the sidewall of the semiconductor layer. The tunneling oxide layer is between the floating gate and the semiconductor substrate and between the first floating gate and the semiconductor layer. A control gate is disposed on the floating gate and an inter-gate dielectric layer is between the control gate and the floating gate and conformally covers the curved sidewall of the first floating gate.

A semiconductor memory device includes a channel layer, a gate electrode spaced apart from the channel layer, a blocking insulating layer between the gate electrode and the channel layer, a tunnel insulating layer between the channel layer and the blocking insulating layer, and nano-particles spaced apart from each other between the tunnel insulating layer and the blocking insulating layer.

The present disclosure relates to a method of forming a flash memory structure. The method includes forming a sacrificial material over a substrate, and forming a plurality of trenches extending through the sacrificial material to within the substrate. A dielectric material is formed within the plurality of trenches. The dielectric material is selectively etched, according to a mask that is directly over the dielectric material, to form depressions along edges of the plurality of trenches. The sacrificial material between neighboring ones of the depressions is removed to form a floating gate recess. A floating gate material is formed within the floating gate recess and the neighboring ones of the depressions.

An electrode structure includes a conductive electrode, the conductive electrode including a first surface, an insulating layer on the conductive electrode, the insulating layer being in contact with the first surface of the conductive electrode, and a nano dot pattern in the conductive electrode and spaced apart from the first surface of the conductive electrode, the nano dot pattern including nano dots arranged in parallel to the first surface of the conductive electrode, and each of the nano dots including a first side surface adjacent to the first surface of the conductive electrode, the first side surface being flat and parallel to the first surface of the conductive electrode, and a second side surface opposite to the first side surface, the second side surface being convex in a direction away from the first surface of the conductive electrode.

The present disclosure relates to an integrated chip structure. The integrated chip structure includes a substrate having a plurality of trenches. An insulating pattern covers bottom surfaces of the plurality of trenches and inner side surfaces of the plurality of trenches. Active patterns are defined by the plurality of trenches. The active patterns are spaced apart from each other in a first direction and are parallel to each other. The first direction is parallel to a top surface of the substrate. At least one of opposite topmost ends of the active patterns has a stepwise portion.