A nitride semiconductor device includes: a substrate; a first semiconductor layer of a first conductivity type disposed above the substrate; a second semiconductor layer disposed above the first semiconductor layer, having a bandgap larger than that of the first semiconductor layer, and undoped; a third semiconductor layer of a second conductivity type disposed above the second semiconductor layer; a fourth semiconductor layer including a channel, and at least partially disposed above the third semiconductor layer; a gate electrode disposed above the first semiconductor layer; a drain electrode disposed below the substrate; and an insulating layer disposed above the gate electrode. The insulating layer covers a bottom and a side wall of a groove provided in an edge termination area of the nitride semiconductor device and penetrating through the third semiconductor layer to reach the second semiconductor layer.

A method for manufacturing a semiconductor device, includes forming source and drain electrodes on a semiconductor layer provided above a substrate; forming a first insulating film covering a surface of the semiconductor layer, between the source and drain electrodes, forming a second insulating film on the first insulating film, forming a mask on the second insulating film, the mask having an opening between the source and drain electrodes in a plan view viewed in a direction perpendicular to a substrate surface, forming a first gate opening in the first insulating film and forming a second gate opening in the second insulating film, by etching the first and second insulating films through the opening, and forming a gate electrode on the first and second insulating films, the gate electrode making a Schottky contact with the semiconductor layer through the first and second gate openings.

A semiconductor device includes multiple GaN units arranged separately from each other in a first direction in a first encapsulation resin. The GaN unit includes a substrate, a GaN transistor arranged at a substrate front surface side of the substrate, and a post arranged on a source pad, a drain pad, and a gate pad of the GaN transistor and exposed from the first encapsulation resin. The post includes a source post formed on the source pad in one of two adjacent ones of the GaN units in the first direction, and a drain post formed on the drain pad in the other one of the two adjacent ones of the GaN units in the first direction. The semiconductor device includes an interconnect layer arranged on an encapsulation front surface and electrically connects the source post and the drain post.

A semiconductor device includes, in this order: first to third channel layers made of a III-V group semiconductor containing Fe and C and a barrier layer made of a III-V group semiconductor having a wider bandgap than a bandgap of the third channel layer. A concentration profile satisfies below-mentioned conditions of: a) Fe concentration in the second channel layer and the third channel layer gradually decreases toward the barrier layer; b) a maximum value of the C concentration in the third channel layer is larger than an average value of the C concentration in the second channel layer; and c) the maximum value of the C concentration in the third channel layer is smaller than a maximum value of a sum of the Fe concentration and the C concentration in the first channel layer.

The present disclosure relates to a semiconductor device, and the semiconductor device includes: a semiconductor substrate; a channel layer provided over the semiconductor substrate and formed of a first nitride semiconductor; a barrier layer provided over the channel layer and formed of a second nitride semiconductor having a larger band gap than the first nitride semiconductor; a metal film selectively formed above the barrier layer; a composite layer provided to be in contact with the metal film and having at least a conductive material and an insulating material; and an insulating film formed over the barrier layer in a region where the metal film and the composite layer are not formed.

A semiconductor device including a HEMT using an N polar plane has a semiconductor laminated structure including a base layer, a barrier layer, and a channel layer. The base layer has a first surface, which is a (000-1) plane, and contains AlN. The barrier layer is formed on the first surface side of the base layer where the first surface is provided, contains AlGaN, and is lattice-relaxed with respect to the base layer. The channel layer is formed on a second surface side of the barrier layer and contains GaN. The barrier layer is not lattice-matched with but is lattice-relaxed with respect to the base layer, and the channel layer is lattice-matched with the barrier layer.

A semiconductor device includes a substrate, a back-barrier layer, a channel layer that has a band gap smaller than a band gap of the back-barrier layer, a first barrier layer that has a band gap larger than the band gap of the channel layer, a second barrier layer that is provided to fill a first recessed portion and has a band gap larger than the band gap of the channel layer, a source electrode, a drain electrode, and a gate electrode. An In composition ratio of the first barrier layer is greater than or equal to 0 and less than an In composition ratio of the second barrier layer. An Al composition ratio of the first barrier layer is greater than or equal to an Al composition ratio of the second barrier layer.

An epitaxial layer (2) is formed on a substrate (1). A field effect transistor (3) is formed on the epitaxial layer (2). A drain pad (8) is formed on the epitaxial layer (2). The drain pad (8) is connected to a drain electrode (5) of the field effect transistor (3). A back surface electrode (13) is formed on a back surface of the substrate (1) and connected to a source electrode (6) of the field effect transistor (3). A wire (16) is bonded to the drain pad (8). A cavity (17) is formed in the substrate (1) directly below the drain pad (8). The cavity (17) is not formed directly below a bonding portion of the wire (16).

Semiconductor devices and associated fabrication methods are disclosed. In one disclosed approach a process for forming a semiconductor device is provided. The process includes: implanting a first region of semiconductor material using a first channeled implant with a first conductivity type; and implanting, after the first channeled implant, a second region of semiconductor material using a second channeled implant with a second conductivity type. The first channeled implant disrupts a crystal structure of the first region of semiconductor material and does not disrupt a crystal structure of the second region of semiconductor material.

A method to process a semiconductor device: processing the substrate forming a first level with a first single-crystal silicon-layer, first transistors, input-and-output (IO) circuits; forming a first metal-layer; forming a second metal-layer including a power-delivery network, where interconnection of the first transistors includes the first metal-layer and the second metal-layer; processing a second level including second transistors with metal gates and a first array of memory-cells; processing a third level including a plurality of third transistors with metal gates and a second array of memory-cells; third level disposed over the second level; forming a fourth metal-layer over a third metal-layer over the third-level; processing a fourth level including a second single-crystal silicon-layer, fourth level is disposed over the fourth metal-layer; forming a via disposed through the second and third levels, connections of the device to external devices includes the IO-circuits; the second level is disposed over the first level.