A tool useful in the manufacture of a semiconductor is disclosed. A mold is providing having an interior defining a planar capillary space. A coating substantially covers at least the planar capillary space of the graphite member. The coating is substantially non-reactive to silicon at temperatures greater than approximately 1420 degrees Centigrade.

A method for manufacturing a photovoltaic device includes a step of depositing one of an amorphous layer of ZnTe and a multilayer stack of Zn and Te adjacent a semiconductor layer. The one of the amorphous layer and the multilayer stack is then subjected to an energy impulse at a temperature equal to or greater than its critical temperature. The energy impulse results in an explosive crystallization to form a polycrystalline layer of ZnTe from the one of the amorphous layer and the multilayer stack.

A photovoltaic cell (1) including a first front collector layer (4), an amorphous silicon layer (6) on the first layer (4) and a second conductive layer (8) on the amorphous silicon layer (6). Electrical connection of the second conductive layer (8) to the first layer (4) is made through the amorphous silicon layer (6) at the periphery of the photovoltaic cell, the electrically conductive layer (8) comprising a positive peripheral bus (8), which is connected to the TCO first layer (4) and to at least one positive connection terminal at one end of the positive peripheral bus, and a negative peripheral bus, which is connected to a negative connection terminal, and the positive and negative peripheral buses being asymmetrical relative to one another, with the positive peripheral bus being longer than the negative peripheral bus.

A method for forming contacts on a photovoltaic device includes forming a heterojunction cell including a substrate, a passivation layer and a doped layer and forming a transparent conductor on the cell. A patterned barrier layer is formed on the transparent conductor and has openings therein wherein the transparent conductor is exposed through the openings in the barrier layer. A conductive contact is grown through the openings in the patterned barrier layer by a selective plating process.

The precursor comprises at least one layer of doped crystalline silicon and a layer of doped amorphous semiconductor material. The method comprises the steps of placing the cell precursor sandwiched between a grounded conducting plate and a plate made of insulating material coated with a conducting layer, then applying a state change electrical voltage (U1) between the conducting layer and ground, the said state change electrical voltage (U1) being designed to bring the Fermi level at the interface between crystalline silicon and amorphous semiconductor material closer to the middle of the band gap of the said amorphous semiconductor material, while at the same time heating the cell precursor to a defect equilibration temperature (T.sub.E), and finally cooling down the cell precursor (10) prior to interrupting the application of the state change electrical voltage (U1).

The present disclosure relates to a heterojunction solar cell, a manufacturing method thereof and a photovoltaic module. The heterojunction solar cell includes a substrate of a first conductivity type, a tunnel layer located on a light-receiving surface of the substrate, and a doped polysilicon layer located on a top surface of the tunnel layer. The doped polysilicon layer has the first conductivity type.

A method for manufacturing a light absorption layer of a thin film solar cell includes: manufacturing a Ib group element-VIa group element binary system nano particle; manufacturing a binary system nano particle slurry of the Ib group element-VIa group element by adding a solution precursor including a solvent, binder and Va group element to the Ib group element-VIa group element binary system nano particle; distributing and mixing the binary system nano particle slurry of the Ib group element-VIa group element; coating the binary system nano particle slurry of the Ib group element-VIa group element on the rear electrode layer; and performing a heat treatment process on the coated nano particle slurry by supplying the VIa group element.

The invention relates to a photoactive semiconductor component, especially a photovoltaic solar cell, having a semiconductor substrate, a carbon-containing SiC layer disposed indirectly upon a surface of the semiconductor substrate, and a passivating intermediate layer disposed indirectly or directly between the SiC layer and semiconductor substrate, and a metallic contact connection disposed indirectly or directly upon a side of the SiC layer facing away from the passivating intermediate layer and in electrically conductive connection with the SiC layer, where the SiC layer has p-type or n-type doping, which is characterized in that the SiC layer partly has a partly amorphous structure and partly has a crystalline structure.

A method of fabricating a semiconductor device includes the following steps. A substrate including an isolation region and a device region is provided. An overall amorphization process is performed on the substrate to form an amorphous region. Here, a minimum depth of the amorphous region is greater than a maximum depth of at least one of the isolation region and the device region, and the amorphous region covers at least one of the isolation region and the device region. A thermal treatment is performed on the amorphous region.

A method for manufacturing a photovoltaic device includes a step of depositing one of an amorphous layer of ZnTe and a multilayer stack of Zn and Te adjacent a semiconductor layer. The one of the amorphous layer and the multilayer stack is then subjected to an energy impulse at a temperature equal to or greater than its critical temperature. The energy impulse results in an explosive crystallization to form a polycrystalline layer of ZnTe from the one of the amorphous layer and the multilayer stack.