A low capacitance transient voltage suppressor with snapback control and a reduced voltage punch-through breakdown mode includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. A set of source regions is formed within a top surface of the second epitaxial layer. Implant regions are formed in the second epitaxial layer, with a first implant region located below the first source region.

A semiconductor device includes a semiconductor body with parallel first and second surfaces and containing hydrogen-related donors. A concentration profile of the hydrogen-related donors vertical to the first surface includes a maximum value of at least 1E15 cm.sup.3 at a first distance to the first surface and does not fall below 1E14 cm.sup.3 over at least 60% of an interval between the first surface and the first distance.

A semiconductor device includes a substrate, an active layer, a transistor, and a capacitor. The active layer is disposed on the substrate, and the active layer is divided into a first portion and a second portion. The transistor and the capacitor are disposed on the substrate. The transistor includes the second portion, a source electrode, a drain electrode, and a gate electrode. The source electrode and the drain electrode are respectively and electrically connected to the second portion. The gate electrode is disposed on the second portion. The capacitor includes the first portion, a first electrode, a first insulating layer, and a second electrode. The first electrode is electrically connected to the first portion and the source electrode. The first insulating layer is disposed on the first portion. The second electrode is disposed on the first insulating layer and is electrically connected to the gate electrode.

Electrical current and/or conductivity in an electrical current channel varies in response to spatiotemporal magnetic flux pattern and/or to variation in electromotive force (EMF). For example, a channel with time-varying electrical conductivity can have induced electrical current variation due to flux pattern resulting from electrical current in another channel or set of channels; the current variation can increase magnetic flux density. The electrical currents can be transient electrical currents, and can cascade to amplify a resulting electromagnetic waveform. A channel can include the channel of a zener or zener-like diode or of a transistor, as well as an extended conductive channel. Channels can be configured in electrical current loops and in various orientations and combinations to obtain current and/or conductivity variation. A transient electrical current can be triggered in a channel, e.g. by an EMF peak, and circuitry with a combination of EMF triggering components can perform logical and timing operation.

Provided is a semiconductor device including: a transistor portion; a current sensing portion which detects a current flowing through the transistor portion; a gate pad which is provided above a semiconductor substrate; and a resistance adjustment portion which is electrically connected to the gate pad and adjusts gate resistances of the transistor portion and the current sensing portion, in which the resistance adjustment portion includes a main adjustment portion which is electrically connected to a gate conductive portion of the transistor portion, and a sense adjustment portion which is electrically connected to a gate conductive portion of the current sensing portion, and each of the main adjustment portion and the sense adjustment portion includes a diode element portion including a plurality of diodes provided in anti-parallel and a resistance portion which is connected to the diode element portion.

Provided is a semiconductor device including: a transistor portion; a current sensing portion which detects a current flowing through the transistor portion; a gate pad which is provided above a semiconductor substrate; and a resistance adjustment portion which is electrically connected to the gate pad and adjusts gate resistances of the transistor portion and the current sensing portion, in which the resistance adjustment portion includes a main adjustment portion which is electrically connected to a gate conductive portion of the transistor portion, and a sense adjustment portion which is electrically connected to a gate conductive portion of the current sensing portion, and each of the main adjustment portion and the sense adjustment portion includes a diode element portion including a plurality of diodes provided in anti-parallel and a resistance portion which is connected to the diode element portion.

A semiconductor device, according to an embodiment, includes a main transistor, a sub transistor that is connected to one terminal of the main transistor, and a resistive element that is connected between another terminal of the main transistor and the sub transistor. The main transistor includes a main channel layer and a barrier layer, which is positioned on the main channel layer and contains a material having an energy band gap different from that of the main channel layer. The sub transistor includes a first sub drift region having a first 2-dimensional electron gas (2DEG) region. The resistive element includes a channel pattern that is electrically connected between a sensing electrode of the sub transistor and a main source electrode of the main transistor, and the channel pattern includes a second sub drift region having a second 2DEG region.

A semiconductor device, according to an embodiment, includes a main transistor, a sub transistor that is connected to one terminal of the main transistor, and a resistive element that is connected between another terminal of the main transistor and the sub transistor. The main transistor includes a main channel layer and a barrier layer, which is positioned on the main channel layer and contains a material having an energy band gap different from that of the main channel layer. The sub transistor includes a first sub drift region having a first 2-dimensional electron gas (2DEG) region. The resistive element includes a channel pattern that is electrically connected between a sensing electrode of the sub transistor and a main source electrode of the main transistor, and the channel pattern includes a second sub drift region having a second 2DEG region.

A module according to this disclosure comprising: a wiring board; a first chip component that has a first electrode portion, a first non-electrode portion, and a second electrode portion and is provided on the wiring board; and a second chip component that has a third electrode portion, a second non-electrode portion, and a fourth electrode portion and is stacked on the first chip component; wherein the second electrode portion is electrically isolated from the third electrode portion and the fourth electrode portion, wherein the second electrode portion is located between the second non-electrode portion and the wiring board.

An antifuse device, including a gate having a gate dielectric layer; a first doping region connected to a first end of the gate; a second doping region connected to a second end of the gate, the second end being opposite to the first end of the gate; a channel that is disposed under the gate and that connects the first doping region and the second doping region; and an interconnection jumper that electrically connects the first doping region and the second doping region.