An antifuse device, including a gate having a gate dielectric layer; a first doping region connected to a first end of the gate; a second doping region connected to a second end of the gate, the second end being opposite to the first end of the gate; a channel that is disposed under the gate and that connects the first doping region and the second doping region; and an interconnection jumper that electrically connects the first doping region and the second doping region.

A deep trench resistor structure and methods of forming the same are described. The structure includes a first trench located in a first dielectric material, a first layer disposed over the first dielectric material, a second layer disposed on the first layer, a second dielectric material disposed over the second layer, and a tunable device in contact with the first layer. The tunable device includes a semiconductor-containing layer in contact with the first layer, a dielectric layer disposed on the semiconductor-containing layer, and a metal-containing layer disposed on the dielectric layer.

There is provided a semiconductor device which includes a plurality of transistor regions; a gate pad provided above a semiconductor substrate; a plurality of gate wiring portions each of which corresponds to each of the plurality of transistor regions; and a plurality of wiring resistance portions each of which is electrically connected to the gate pad and corresponds to each of the plurality of gate wiring portions. The plurality of gate wiring portions may include a gate metal layer provided above the semiconductor substrate and a gate runner provided below the gate metal layer. A built-in resistance portion may be electrically connected between the gate pad and the plurality of gate wiring portions.

There is provided a semiconductor device which includes a plurality of transistor regions; a gate pad provided above a semiconductor substrate; a plurality of gate wiring portions each of which corresponds to each of the plurality of transistor regions; and a plurality of wiring resistance portions each of which is electrically connected to the gate pad and corresponds to each of the plurality of gate wiring portions. The plurality of gate wiring portions may include a gate metal layer provided above the semiconductor substrate and a gate runner provided below the gate metal layer. A built-in resistance portion may be electrically connected between the gate pad and the plurality of gate wiring portions.

An antifuse device, including a gate having a gate dielectric layer; a first doping region connected to a first end of the gate; a second doping region connected to a second end of the gate, the second end being opposite to the first end of the gate; a channel that is disposed under the gate and that connects the first doping region and the second doping region; and an interconnection jumper that electrically connects the first doping region and the second doping region.

An antifuse device, including a gate having a gate dielectric layer; a first doping region connected to a first end of the gate; a second doping region connected to a second end of the gate, the second end being opposite to the first end of the gate; a channel that is disposed under the gate and that connects the first doping region and the second doping region; and an interconnection jumper that electrically connects the first doping region and the second doping region.

A method for controlling a concentration of donors in an Al-alloyed gallium oxide crystal structure includes implanting a Group IV element as a donor impurity into the crystal structure with an ion implantation process and annealing the implanted crystal structure to activate the Group IV element to form an electrically conductive region. The method may further include depositing one or more electrically conductive materials on at least a portion of the implanted crystal structure to form an ohmic contact. Examples of semiconductor devices are also disclosed and include a layer of an Al-alloyed gallium oxide crystal structure, at least one region including the crystal structure implanted with a Group IV element as a donor impurity with an ion implantation process and annealed to activate the Group IV element, an ohmic contact including one or more electrically conductive materials deposited on the at least one region.

In a contact hole, a first side surface of an interlayer insulating film is separated from a second side surface of a first conductive film so that a part of an upper surface of the first conductive film is exposed from the interlayer insulating film. In the contact hole, a third side surface of an insulating film is separated from the second side surface of the first conductive film so that a part of the lower surface of the first conductive film is exposed from the insulating film. A plug includes a silicide layer formed on the second side surface of the first conductive film, a barrier metal film formed on the silicide layer, and a second conductive film formed on the barrier metal film.

In a contact hole, a first side surface of an interlayer insulating film is separated from a second side surface of a first conductive film so that a part of an upper surface of the first conductive film is exposed from the interlayer insulating film. In the contact hole, a third side surface of an insulating film is separated from the second side surface of the first conductive film so that a part of the lower surface of the first conductive film is exposed from the insulating film. A plug includes a silicide layer formed on the second side surface of the first conductive film, a barrier metal film formed on the silicide layer, and a second conductive film formed on the barrier metal film.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a valley inwardly positioned on a top surface of the substrate; a programmable insulating layer conformally positioned on the valley and including a V-shaped cross-sectional profile; and a top electrode positioned on the programmable insulating layer. The programmable insulating layer is configured to be blown out under a programming voltage.