The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Junction field-effect transistors including inorganic channels and organic gate junctions are used in some applications for forming high resolution active matrix displays. Arrays of such junction field-effect transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes.

The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

The present disclosure relates to a semiconductor device and a method of manufacturing semiconductor device. The present disclosure relates particularly to MOSFET transistors. A semiconductor device according to the disclosure including: a first-conductivity-type substrate, a first-conductivity-type epitaxy layer including a JFET region and a second-conductivity-type shield region, two well regions including two source regions, gate oxide including a gate, a drain adjacent to the first-conductivity-type substrate, the first-conductivity-type substrate is adjacent to the first-conductivity-type epitaxy layer, the two well regions are adjacent to the first-conductivity-type epitaxy layer, the JFET region is located between the two well regions, the source contact region is the outermost layer and is adjacent to the two source regions, and the gate oxide is adjacent to the two well regions, the two source regions, and the JFET region.

The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

A method of forming a double-gated junction field effect transistors (JFET) and a tri-gated metal-oxide-semiconductor field effect transistor (MOSFET) on a common substrate is provided. The double-gated JFET is formed in a first region of a substrate by forming a semiconductor gate electrode contacting sidewall surfaces of a first channel region of a first semiconductor fin and a top surface of a portion of a first fin cap atop the first channel region. The tri-gated MOSFET is formed in a second region of the substrate by forming a metal gate stack contacting a top surface and sidewall surfaces of a second channel region of a second semiconductor fin.

The present application discloses a method for manufacturing a metal gate of a PMOS, comprising: step 1, forming a P-type work function metal layer; step 2, depositing an N-type work function metal layer by means of a PVD process, wherein over a bottom surface of a gate trench, the N-type work function metal layer has a hill profile; step 3, forming a first top barrier metal sublayer by means of a conformal growth process, wherein the first top barrier metal sublayer completely fills a sharp corner area of the N-type work function metal layer at a corner of the gate trench; step 4, growing a second top barrier metal sublayer by means of a PVD bombardment process; step 5, forming a third top barrier metal sublayer and a fourth top barrier metal sublayer; and step 6, forming a metal conductive material layer.

A transistor that may include a substrate. A drift layer on the substrate. The drift layer having a recessed portion and a protruding portion. A well layer within the recessed portion of the drift layer and sides of the protruding portion of the drift layer. A source layer within a portion of the recessed portion of the drift layer and the protruding portion of the drift layer. A JFET layer within the protruding portion of the drift layer. An insulating layer over a portion of the source layer and over a portion of the well layer on the sides of the protruding portion of the drift layer. A gate electrode over a portion of the insulating layer.

A method for manufacturing an optical device includes providing a carrier waver, provide a first substrate having a first surface region, and forming a first gallium and nitrogen containing epitaxial material overlying the first surface region. The first epitaxial material includes a first release material overlying the first substrate. The method also includes patterning the first epitaxial material to form a plurality of first dice arranged in an array; forming a first interface region overlying the first epitaxial material; bonding the first interface region of at least a fraction of the plurality of first dice to the carrier wafer to form bonded structures; releasing the bonded structures to transfer a first plurality of dice to the carrier wafer, the first plurality of dice transferred to the carrier wafer forming mesa regions on the carrier wafer; and forming an optical waveguide in each of the mesa regions, the optical waveguide configured as a cavity to form a laser diode of the electromagnetic radiation.

A semiconductor device includes a drift layer including silicon carbide and having a first conductivity type, a channel layer on the drift layer, the channel layer including silicon carbide and having the first conductivity type, and a source layer on the channel layer, the source layer including silicon carbide and having the first conductivity type. The device includes first and second trenches extending through the source layer and at least partially into the channel layer. The first and second trenches define a mesa therebetween having a mesa sidewall adjacent the channel layer. A heterojunction layer is in the first trench. The heterojunction layer includes a semiconductor material having a second conductivity type opposite the first conductivity type, wherein the heterojunction layer forms a PN heterojunction with silicon carbide.