Provided is a semiconductor device including: a first trench portion having a predetermined first trench length; a second trench portion having a second trench length longer than the first trench length; a first gate runner portion configured to be electrically connected to an end portion of the first trench portion; and a second gate runner portion configured to be electrically connected to the first gate runner portion and electrically connected to an end portion of the second trench portion. A resistivity per unit length of the first gate runner portion is larger than a resistivity per unit length of the second gate runner portion.

Provided is a semiconductor device including a semiconductor substrate; a transistor portion provided in the semiconductor substrate; a current sensing portion for detecting current flowing through the transistor portion; an emitter electrode set to an emitter potential of the transistor portion; a sense electrode electrically connected to the current sensing portion; and a Zener diode electrically connected between the emitter electrode and the sense electrode. Provided is a semiconductor device fabricating method including providing a transistor portion in a semiconductor substrate; providing a current sensing portion for detecting current flowing through the transistor portion; providing an emitter electrode set to an emitter potential of the transistor portion; providing a sense electrode electrically connected to the current sensing portion; and providing a Zener diode electrically connected between the emitter electrode and the sense electrode.

The reverse-conducting IGBT device is formed in a die having a substrate of a first conductivity type accommodating an IGBT in a first portion and a diode in a second portion. The IGBT has a body structure; a source region; a trench-gate region; a first contact structure; and an emitter region, of the second conductivity type. The diode has an anode region, of the second conductivity type, facing the first main surface; and a second contact structure, on the first main surface and in direct electrical contact with the anode region. The second contact structure is coupled with the first contact structure and is by a barrier layer extending above the first main surface of the substrate, in contact with the anode region, and by a diode contact plug, of metal, above and in contact with the barrier layer.

A power conversion device configured to convert electric power using a semiconductor device includes a MOS controlled diode 1 made up of an n.sup.+ layer 11, an n.sup. layer 12, a p.sup. layer 13, a p.sup.+ layer 14, a cathode electrode 21, anode electrodes 22 and 220, and gate electrodes 23 and a voltage applying unit configured to apply forward voltage between the anode electrodes 22 and 220 and the cathode electrode 21 during a forward direction, to apply a reverse voltage between the anode electrodes 20 and 220 and the cathode electrode 21 during a reverse recovery, and to control a potential of the gate electrode 23 to a potential at which an inversion layer is formed in a third semiconductor layer with respect to a potential of the anode electrodes 22 and 220 before the reverse recovery. In this way, a power conversion device, a method of controlling a power conversion device, a semiconductor device, and a method of controlling a semiconductor device that are capable of further reducing power loss are provided.

According to the present disclosure, a semiconductor device includes a semiconductor substrate, a first metal layer provided above the semiconductor substrate, a second metal layer provided above the first metal layer and containing Ni as a material and a third metal layer provided above the second metal layer and containing Cu or Ni as a material, wherein the second metal layer has a Vickers hardness of 400 Hv or more and is harder than the third metal layer, and the third metal layer is harder than the first metal layer.

Provided is a semiconductor device comprising a semiconductor substrate that includes a transistor region; an emitter electrode that is provided on the semiconductor substrate; a first dummy trench portion that is provided on the transistor region of the semiconductor substrate and includes a dummy conducting portion that is electrically connected to the emitter electrode; and a first contact portion that is a partial region of the transistor region, provided between an end portion of a long portion of the first dummy trench portion and an end portion of the semiconductor substrate, and electrically connects the emitter electrode and a semiconductor region with a first conductivity type provided in the transistor region.

Provided is a semiconductor device including: a drift region of a first conductivity type which is provided in a semiconductor substrate; an emitter region of the first conductivity type which is provided at a front surface of the semiconductor substrate, and which has a doping concentration higher than that of the drift region; a plurality of trench portions which are provided above the drift region; a trench contact portion which is provided in a mesa portion between the plurality of trench portions; and a plug region of a second conductivity type which is provided in contact with a lower end of the trench contact portion. The trench contact portion may have a main trench contact which extends in a trench extension direction in a top view, and a sub-trench contact which extends from the main trench contact in a direction different from the trench extension direction in the top view.

Provided is a manufacturing method for a semiconductor device including forming a first electrode layer on a front surface of a wafer, implanting, into an outer peripheral region of the front surface of the wafer, a heavy ion of an element in third and subsequent rows of a periodic table, forming an oxide film in the outer peripheral region into which the heavy ion has been implanted, and forming a second electrode layer on the first electrode layer by plating. A dose of the heavy ion may be 1E15 cm.sup.2 or more. A depth of an implantation range of the heavy ion into the wafer may be 0.02 m or more. The heavy ion may be an As ion, a P ion, or an Ar ion.

To realize a highly reliable IGBT that suppresses the bipolar degradation by preventing the occurrence of a defect on a boundary between a contact region and a silicide layer. As a means to realize the above, a semiconductor device includes: a collector region that is formed on a lower surface of a semiconductor substrate and forms an IGBT; and a collector electrode that is formed on a lower surface of the collector region via a silicide layer. The collector region and the silicide layer contains aluminum, first metal being more easily bondable to silicon than aluminum, and second metal being more easily bondable to carbon than aluminum.

According to one embodiment, wafer includes a substrate including silicon carbide. The substrate includes a first face and a second face. The substrate includes a first region between the second face and the first face in a first direction from the second face to the first face, a second region between the second face and the first region in the first direction, and a third region between the first region and the first face in the first direction. The first region includes a first element including at least one selected from the group consisting of fluorine and oxygen. A first concentration of the first element in the first region is higher than a second concentration of the first element in the second region, and higher than a third concentration of the first element in the third region.