According to one embodiment, wafer includes a substrate including silicon carbide. The substrate includes a first face and a second face. The substrate includes a first region between the second face and the first face in a first direction from the second face to the first face, a second region between the second face and the first region in the first direction, and a third region between the first region and the first face in the first direction. The substrate includes nitrogen. The first region includes a first element including at least one selected from the group consisting of phosphorus and arsenic. A first concentration of the first element in the first region is higher than a second concentration of the first element in the second region, and higher than a third concentration of the first element in the third region.

An upper electrode is separated from a lower electrode inside a trench by an intermediate insulating film. A first resistor is connected between the upper electrode and the gate electrode. A second resistor is connected between the lower electrode and the gate electrode. Gate-emitter capacitance of the lower electrode is smaller than gate-emitter capacitance of the upper electrode.

The semiconductor device includes a semiconductor layer which has a main surface, a switching device which is formed in the semiconductor layer, a first electrode which is arranged on the main surface and electrically connected to the switching device, a second electrode which is arranged on the main surface at an interval from the first electrode and electrically connected to the switching device, a first terminal electrode which has a portion that overlaps the first electrode in plan view and a portion that overlaps the second electrode and is electrically connected to the first electrode, and a second terminal electrode which has a portion that overlaps the second electrode in plan view and is electrically connected to the second electrode.

A method for producing a power semiconductor component includes: providing a power semiconductor partial structure having an insulating layer arranged on an upper side of a semiconductor body and a contact hole proceeding from an upper side of the insulating layer, extending at least partly within the insulating layer and configured for electrical contacting of a contact region below the upper side; at least partly covering the upper side and a surface of the contact hole with an adhesion promoter layer; at least partly covering the adhesion promoter layer with a tungsten-comprising layer having a first thickness dimensioned such that the tungsten-comprising layer fills the contact hole; removing part of the tungsten-comprising layer in a region of the upper side such that the tungsten-comprising layer has a second thickness in the upper side region that is less than the first thickness; and applying a connection layer to the tungsten-comprising layer.

Provided is a semiconductor device which includes a diode portion, the semiconductor device includes: a drift region of a first conductivity type which is provided in a semiconductor substrate; a plurality of trench portions which extend in a predetermined trench extending direction on a front surface side of the semiconductor substrate; and a front-surface electrode portion which is provided above a front surface of the semiconductor substrate, the diode portion includes a plug region of a second conductivity type which is provided in the semiconductor substrate and in contact with the front-surface electrode portion, and a first conductivity type mesa region of the first conductivity type which is in contact with the plug region in a mesa portion between the plurality of trench portions.

According to one embodiment, a semiconductor device includes first to third electrodes, a first wiring member, a semiconductor member, and an insulating member. The first wiring member includes a first extending portion. A part of the third electrode is between the first electrode and the first extending portion. An other part of the third electrode is between the first and second electrodes. The semiconductor member is provided between the first and second electrodes and between the first electrode and the first extending portion. The semiconductor member includes first to sixth semiconductor regions. The first semiconductor region includes first and second partial regions. The first partial region is located between the first electrode and the third electrode. The insulating member includes the first insulating region. The first insulating region is provided between the third electrode and the semiconductor member.

A semiconductor device includes a first electrode; a first semiconductor region of a first conductivity type on the first electrode and including a first region and a second region positioned around the first region; a second semiconductor region of a second conductivity type on the first region; a third semiconductor region of the first conductivity type on the second semiconductor region; a gate electrode facing the second semiconductor region via a gate insulating layer; a fourth semiconductor region of the second conductivity type on the second region and spaced apart from the second semiconductor region; a second electrode provided on the third semiconductor region via a first contact; a third electrode provided on the fourth semiconductor region via a second contact. The first and second contacts each include a titanium-containing layer, a titanium nitride-containing layer on the titanium-containing layer, and a tungsten-containing layer on the titanium nitride-containing layer.

Provided is a semiconductor device including a MOS gate structure provided in a semiconductor substrate, including: an interlayer dielectric film which includes a contact hole and is provided above the semiconductor substrate; a conductive first barrier metal layer provided on side walls of the interlayer dielectric film in the contact hole; a conductive second barrier metal layer stacked on the first barrier metal layer in the contact hole; and a silicide layer provided on an upper surface of the semiconductor substrate below the contact hole, in which the first barrier metal layer is more dense than the second barrier metal layer, and a film thickness thereof is 1 nm or more and 10 nm or less.

A lateral silicon carbide power semiconductor device is disclosed. The device comprises a substrate and a silicon carbide semiconductor structure disposed on the substrate and having a principal surface. The semiconductor structure comprises a layer of first conductivity type disposed on the substrate, and a layer-shaped drift region of a second conductivity type, which is opposite to the first conductivity type, disposed directly on the layer so as to form an interface between the layer and the drift region. The drift region runs laterally along the principal surface between first and second ends. Doping in the drift region and the layer are arranged so as to deplete the drift region. The device comprises a first contact region to the drift region. The device comprises a second contact region to the second end of the drift region which is highly doped, which is of the first or second conductivity type which adjoins the second end of the drift region, is disposed in the drift region or in a region which adjoins the second end of the drift region The device comprises a highly-doped region of the first conductivity type extending into the semiconductor structure from the principal surface and adjoining the first end of the drift region, wherein the highly-doped region has a thickness greater than the drift region.

In a contact hole, a first side surface of an interlayer insulating film is separated from a second side surface of a first conductive film so that a part of an upper surface of the first conductive film is exposed from the interlayer insulating film. In the contact hole, a third side surface of an insulating film is separated from the second side surface of the first conductive film so that a part of the lower surface of the first conductive film is exposed from the insulating film. A plug includes a silicide layer formed on the second side surface of the first conductive film, a barrier metal film formed on the silicide layer, and a second conductive film formed on the barrier metal film.