A method for manufacturing a silicon carbide device includes providing a silicon carbide wafer and manufacturing a mask layer on top of the silicon carbide wafer. Further, the method includes structuring the mask layer at an edge of a silicon carbide device to be manufactured, so that the mask layer includes a bevel at the edge of the silicon carbide device to be manufactured. Additionally, the method includes etching the mask layer and the silicon carbide wafer by a mutual etching process, so that the bevel of the mask layer is reproduced at the edge of the silicon carbide device.

Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described that includes: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; and a gate positioned between the first and second regions, such that the first region is on a first side of the memory cell relative to the gate and the second region is on a second side of the memory cell relative to the gate; wherein performance characteristics of the first side are different from performance characteristics of the second side.

Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described that includes: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; and a gate positioned between the first and second regions, such that the first region is on a first side of the memory cell relative to the gate and the second region is on a second side of the memory cell relative to the gate; wherein performance characteristics of the first side are different from performance characteristics of the second side.

A vertical semiconductor triode includes a first layer of semiconductor material, the first layer including first and second surfaces, the first surface being in contact with a first electrode forming a Schottky contact.

A vertical semiconductor triode includes a first layer of semiconductor material, the first layer including first and second surfaces, the first surface being in contact with a first electrode forming a Schottky contact.