H10D48/3835

QUANTUM TELEPORTATION NETWORK SYSTEM USING ELECTRONICALLY DRIVEN GRAPHENE WAVEGUIDES

A system includes N-distant independent plasmonic graphene waveguides. The N-distant independent plasmonic graphene waveguides are used to generate an N-partite continuous variable entangled state.

ARCHITECTURE FOR COUPLING QUANTUM BITS USING LOCALIZED RESONATORS

A technique relates a superconducting microwave cavity. An array of posts has different heights in the cavity, and the array supports a localized microwave mode. The array of posts includes lower resonant frequency posts and higher resonant frequency posts. The higher resonant frequency posts are arranged around the lower resonant frequency posts. A first plate is opposite a second plate in the cavity. One end of the lower resonant frequency posts is positioned on the second plate so as to be electrically connected to the second plate. Another end of the lower resonant frequency posts in the array is open so as not to form an electrical connection to the first plate. Qubits are connected to the lower resonant frequency posts in the array of posts, such that each of the qubits is physically connected to one or two of the lower resonant frequency posts in the array of posts.

ELECTRON HOLE SPIN QUBIT TRANSISTOR, AND METHODS FOR FORMING A ELECTRON HOLE SPIN QUBIT TRANSISTOR
20250169121 · 2025-05-22 ·

The present inventive concept relates to a spin qubit transistor (100) comprising a base layer (102), a first qubit comprising, a first computing semiconductor island (106) and a first readout semiconductor island (108) arranged with a distance in the range of 3-10 nm therebetween, a second qubit comprising, a second computing semiconductor island (110) and a second readout semiconductor island (112) arranged with a distance in the range of 3-10 nm therebetween, wherein each of said semiconductor islands has a size causing each of said semiconductor islands to exhibit 3-dimensional quantum confinement of a single electron hole, and wherein each of said semiconductor islands forms a semiconductor heterojunction with the base layer. Each of the semiconductor islands has a corresponding gate (G1-G4), for modulation of the computing islands or readout of the readout islands. Said first computing semiconductor island and said second computing semiconductor island are configured to have a unique resonance frequency respectively. A control electrode arrangement (B) between the computing and the readout islands controls the coupling between the qubits. The present inventive concept further comprises a method for forming a spin qubit transistor and a quantum computer comprising at least one spin qubit transistor.

ULTRA-CLEAN VAN DER WAALS HETEROSTRUCTURES AND TECHNIQUES OF FABRICATION THEREOF

Disclosed are heterostructures that deploy one or more ultra-clean layers of van der Waals materials (VdW heterostructures). Further disclosed are techniques of fabricating VdW heterostructures that include patterning a conducting layer positioned on a substrate, separating, using a curved lifting surface, the patterned conducting layer from the substrate, and transferring the patterned conducting layer to a receiving stack of one or more layers while removing residual contaminants.

METHOD FOR CALIBRATING AND/OR ASSISTING IN THE DESIGN OF A SPIN-QUBIT OR TWO-LEVEL QUANTUM SYSTEM AND QUANTUM COMPONENT
20250190832 · 2025-06-12 ·

The invention relates to a method for calibrating a two-level spin quantum system coupled to a microwave cavity by a symmetric magnetic field and an antisymmetric magnetic field in the form of a double quantum dot comprising a left dot and a right dot, which system is subjected to a bias voltage, the method being characterized by the following steps: setting the bias voltage () to zero volts; determining a wave function p of each of the quantum dots; calculating and/or setting the antisymmetric das and symmetric as magnetic coupling constants, calculating and/or setting the tunnel coupling constant, and/or the symmetric magnetic coupling constant s and/or the antisymmetric magnetic coupling constant as.

Filter for laminated circuit assembly

A laminated circuit assembly for filtering signals in one or more signal lines in, for instance, a quantum computing system is provided. In one example, the laminated circuit assembly includes one or more signal lines disposed within a substrate in a first direction. The laminated circuit assembly includes a dielectric portion of the substrate. The laminated circuit assembly includes a filter portion of the substrate extending in a first direction and containing a frequency absorbent material providing less attenuation to a first signal of a first frequency than to a second signal of a second, higher frequency. The filter portion is configured to attenuate infrared signals passing through the one or more signal lines.

METHOD AND DEVICE FOR ADDRESSING QUBITS, AND METHOD FOR PRODUCING THE DEVICE

A method of addressing at least one qubit to be addressed in a set of two or more qubits in diamond, comprises; exposing the qubit to be addressed to an electromagnetic field; and at the same time exposing another qubit of the set of two or more qubits to an electromagnetic counter field in such a way that the electromagnetic field has no effect on the other qubit or that the electromagnetic field has a different effect on the other qubit than on the qubit to be addressed.

Array of quantum dots with spin qubits

An elementary cell for a two-dimensional array of quantum dots, said elementary cell extending along a main plane and including: a plurality of sites occupied by quantum dots capable of confining at least one spin qubit and including at least: a first quantum dot, a second quantum dot adjacent to the first quantum dot in a first direction of the main plane, and a third quantum dot adjacent to the first quantum dot in a second direction of the main plane; and a first blocking site adjacent to the second and third quantum dots, towards which a spin qubit cannot be displaced.

Device and method for fabricating highly integrated and miniaturized silicon quantum bit device including at least a tunnel field effect transistor with reduced leakage current, inter-quantum bit coupler, and quantum gate operating mechanism that are formed by self-alignment

To suppress a leakage current caused by a gate of a tunnel field effect transistor included in a silicon spin quantum bit device, the silicon spin quantum bit device is provided including a tunnel field effect transistor having a gate, a source, and a drain, a quantum gate operation mechanism for spin control, which is provided under the tunnel field effect transistor, and an inter-qubit coupler for coupling a channel of the tunnel field effect transistor with a channel of a tunnel field effect transistor included in another quantum bit device. Further, the gate is made wider in width than the channel and is partly formed on the inter-qubit coupler.

ENGINEERED QUANTUM PROCESSING ELEMENTS

Engineered quantum processing elements are disclosed. The engineered quantum processing element includes a dopant dot embedded in a semiconductor substrate. A dielectric material forms an interface with the semiconductor substrate. The dopant dot includes a plurality of dopant atoms and one or more electrons/holes confined within the dopant dot. The geometrical configuration of the plurality of dopant atoms with respect to the semiconductor substrate is engineered to achieve optimal linear hyperfine Stark coefficients. Further, aspects of the present disclosure are directed to methods of fabricating such engineered quantum processing elements.