An electronic device includes a pair of depletion gates, an accumulation gate, and a conductive resonator. The depletion gates are spaced apart from each other. The accumulation gate is over the depletion gates. The conductive resonator is over the depletion gates and the accumulation gate. The conductive resonator includes a first portion, a second portion, and a third portion. The first portion and the second portion are on opposite sides of the accumulation gate. The third portion interconnects the first and second portions of the conductive resonator and across the depletion gates. A bottom surface of the first portion of the conductive resonator is lower than a bottom surface of the accumulation gate.

The present disclosure provides a two-dimensional scalable superconducting qubit structure and a method for controlling a cavity mode thereof. The two-dimensional scalable superconducting qubit structure includes: a superconducting qubit chip comprising a plurality of two-dimensionally distributed and scalable qubits; a capacitor part of each of the qubits has at least five arms distributed two-dimensionally, two of the at least five arms in each qubit are respectively connected with a read coupling circuit and a control circuit, and the other at least three arms are coupled with adjacent qubits through a coupling cavity.

The invention provides a spin qubit-type semiconductor device capable of achieving both high-speed spin manipulation and high integration, and an integrated circuit for the spin qubit-type semiconductor device. The spin qubit-type semiconductor device includes a body comprised of at least one of a semiconductor layer itself formed with a quantum dot and a structural portion arranged around the semiconductor layer, a gate electrode arranged at a position on the semiconductor layer, which faces the quantum dot, at least one micro magnet wholly or partly embedded in the body so that a first position condition in which the micro magnet is at a position near the quantum dot, a second position condition in which the position of a lower end of the micro magnet is located below the gate electrode, and a third position condition in which when viewed from above the body, the micro magnet is arranged at a position having no rotational symmetry with the quantum dot as the center of rotation are satisfied, and a static magnetic field applying unit capable of applying a static magnetic field to the quantum dot and the micro magnet.

A structure for cooling a component of a quantum device by circulating a given current between a first contact element with the component and a second contact element with the component, the first contact element comprising at least one given superconducting metal material, in particular at a given temperature less than 2K, and being in contact by a first end with a first semiconductor portion of said component so as to form with the first semiconductor portion at least one cooling tunnel junction.

Gate-controlled quantum dots based on silicon-germanium (SiGe) alloy heterostructures are provided. Also provided are quantum computing systems incorporating the gate-controlled quantum dots. The quantum dots are formed in a semiconductor heterostructure in which a SiGe alloy quantum well is sandwiched between SiGe alloy barriers or between Ge barriers. The presence of germanium in the quantum dots increases the average valley splitting for quantum dots confined in the SiGe. As a result, the yield of quantum dots having a sufficiently high valley splitting for device applications is increased by the use of a SiGe alloy in the quantum well.

A qubit device includes first and second linear qubit arrays. Each qubit array includes a semiconductor substrate, control gates configured to define a single row of quantum dots along the substrate, and nanomagnets distributed along the row of quantum dots such that a nanomagnet is arranged at every other pair of quantum dots of the row of quantum dots. Each nanomagnet has an out-of-plane magnetization with respect to the substrate, where the rows of the first and second arrays extend in a common row direction and are separated along a direction transverse to the row direction. The qubit device further includes superconducting resonators connecting pairs of quantum dots between the first and second arrays. Each pair of quantum dots in the first array is configured to couple with a superconducting resonator of the first set to connect with a different pair of quantum dots of the second array.

A method for making a qubit device comprising a chiral nanocrystal includes forming a gate electrode on a non-conducting substrate, forming an insulating layer over the back gate electrode, immobilizing a bottom face of a semiconductor nanocrystal onto the insulating layer, and placing two or more electrodes on, or in apposition to, a top face of the semiconductor nanocrystal.

A device includes depletion gates, an accumulation gate, and a conductive resonator. The depletion gates extend lengthwise along a first direction over a substrate. The accumulation gate includes a conductive bridge extending lengthwise along a second direction across the depletion gates and spaced apart from the depletion gates. The conductive resonator is over the accumulation gate. The conductive resonator includes a conductive bridge extending lengthwise along the second direction across the depletion gates and spaced apart from the accumulation gate.

Qubit arrays having substrates that are engineered to suppress correlated dephasing errors, correlated relaxation errors, or both are provided. Also provided are quantum circuits incorporating the qubit arrays and quantum computers incorporating the quantum circuits. The engineered substrates can be used to suppress noise and correlated errors in any qubit array that suffers from charge fluctuations or other noise that creates a non-equilibrium, error-producing state in the qubit array.

A semiconductor device structure includes a first source/drain (S/D) feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a first silicide layer in contact with the first surface of the first S/D feature, a plurality of semiconductor channel layers vertically stacked, each semiconductor layer being in contact with the sidewall of the first S/D feature. The structure also includes a gate dielectric layer surrounding at least one semiconductor layer, a dielectric structure comprising a first side and a second side, the first side being in contact with the gate dielectric layer and the second surface of the first S/D feature. The structure further includes an interlayer dielectric (ILD) in contact with the second surface of the dielectric structure.