A quantum device comprising an array of quantum dots is disclosed. The quantum device comprises a silicon layer in which quantum dots (201) can be induced by respective gates; gates of the inducible quantum dots (201) for controlling an electrical potential that define the induced quantum dots (201); and integrated circuit elements (204), in particular comprising floating gate field effect transistors, for controlling the voltages of the respective gates, the integrated circuit elements (204) having non-volatile resistance value, RF, which are tunable. The integrated circuit elements (204) have input voltages (Vin) and an output voltages (Vout), wherein the output voltages are dependent on the input voltages and the non-volatile resistance values RF of the different integrated circuit elements. The integrated circuit elements (204) are electrically connected such that their respective output voltages are applied to the gates of the respective inducible quantum dot (201). The gates of the individual quantum dots can thus be addressed using a single input voltage.

Techniques for implementing a QRAM by routing quantum information through multiple modes of a bosonic system are described. According to some aspects, a single bosonic system may be configured to maintain quantum information in a large number of independent modes at the same time. Suitable operations upon these modes may allow a quantum address value to be routed to modes associated with respective bits such that the only modes altered by the operations are those associated with the addresses being accessed. These modes may be operated upon based on the stored values then extracted to obtain the desired correlated superposition of the stored bit values in the addresses. The bits stored at the address locations may be classical bits, or may be qubits.

A silicon-based quantum device for confining charge carriers is provided. The device comprises: a substrate having a first planar region 137; a silicon layer 32 which forms part of the substrate and includes a step 33 with an edge 34 and a second planar region 135, wherein the second planar region 135 is substantially parallel to and offset from the first planar region 137; a first electrically insulating layer 42 provided on the silicon layer 32, overlying the step 33; a first metallic layer 51, provided on the first electrically insulating layer 42, overlying the step 33, arranged to be electrically connected such that a first confinement region 10 can be induced in which a charge carrier or charge carriers can be confined at the edge 34; and a second metallic layer 52, provided overlying the second planar region 135 of the silicon layer, wherein the second metallic layer is: electrically separated from the first metallic layer 51; and arranged to be electrically connected such that a second confinement region 11 can be induced in which a charge carrier or charge carriers can be confined only in the second planar region 135 of the silicon layer 32 under the second metallic layer 52, and the first confinement region 10 is couplable to the second confinement region 11; wherein the first confinement region 10 is displaced from the second confinement region 11 in a direction that is perpendicular to the edge 34. A method of assembling a silicon-based quantum device and a method of using a silicon-based quantum device are also provided.

A charge sensor according to the present disclosed technology includes a quantum dot to have a first end connected to an input terminal via a first tunnel junction and a second end connected to an output terminal via a second tunnel junction, and an inductor connected in parallel to the quantum dot.

A method is provided, including: applying a magnetic field according to a two-qubit gate operation performed with a quantum device; transmitting a voltage signal to a gate structure, arranged above first and second quantum dots in the quantum device, to generate a coupling signal that includes a first sine squared wave; and performing, by the magnetic field and the coupling signal, the two-qubit gate operation to the first and second qubits in the first and second quantum dots.

The disclosure describes an adaptive and optimal imaging of individual quantum emitters within a lattice or optical field of view for quantum computing. Advanced image processing techniques are described to identify individual optically active quantum bits (qubits) with an imager. Images of individual and optically-resolved quantum emitters fluorescing as a lattice are decomposed and recognized based on fluorescence. Expected spatial distributions of the quantum emitters guides the processing, which uses adaptive fitting of peak distribution functions to determine the number of quantum emitters in real time. These techniques can be used for the loading process, where atoms or ions enter the trap one-by-one, for the identification of solid-state emitters, and for internal state-detection of the quantum emitters, where each emitter can be fluorescent or dark depending on its internal state. This latter application is relevant to efficient and fast detection of optically active qubits in quantum simulations and quantum computing.

A quantum information processing device including a semiconductor substrate. An optical resonator is coupled to the substrate. The optical resonator supports a first photonic mode with a first resonator frequency. The quantum information processing device includes a non-gaseous chalcogen donor atom disposed within the semiconductor substrate and optically coupled to the optical resonator. The donor atom has a transition frequency in resonance with the resonator frequency. Also disclosed herein are systems, devices, articles and methods with practical application in quantum information processing including or associated with one or more deep impurities in a silicon substrate optically coupled to an optical structure.

A Qbit spin quantum device includes juxtaposed first and second semiconducting portions, the semiconducting portions being formed in a surface layer of a semiconductor-on-insulator type substrate and disposed on an insulating layer of the substrate, the substrate being fitted with a semiconducting support layer such that the insulating layer is arranged between the support layer and the surface layer, and several pairs of front control gates, each pair being formed respectively of first and second front control gates covering a region of the first and second semiconducting portions to form first and second quantum islands, respectively. An insulating region is provided between the first and second quantal islands to enable electrostatic coupling between the first and second quantum islands. The quantum device includes a back conductive electrode vertically aligned with a coupling insulating region and being formed of a region of metal-semiconductor material alloy arranged in the support layer.

An array of gate structures is produced on a planar surface, the array being suitable for the production of a spin qubit quantum dot device. The gate structures include alternately arranged structures of a first and second type. According to the example embodiments, electrical connections to the gate structures of the first and second type are produced in separate process step sequences. The connections to the first gate type include the formation of first conductive lines running essentially parallel to the planar surface and connected to the gate structures of the first type by first via connections. Before producing similar connections to the gate structures of the second type, a conformal dielectric layer is formed on the first conductive lines. The conformal layer is configured so that it forms a protective spacer on the sidewalls of the first conductive lines during processing of the second conductive lines, to avoid shorting.

A fabrication method for a semiconductor structure with a hole spin qubit includes: providing a substrate; growing a germanium quantum well on the substrate, in which the germanium quantum well is an inclined quantum well structure grown in a [110] direction, and the germanium quantum well is grown by a complementary metal oxide semiconductor process; and fabricating a two-dimensional gate-defined quantum dot in the germanium quantum well.