A thin-film piezoelectric material elements are arranged on a thin-film piezoelectric material substrate. The thin-film piezoelectric material substrate includes an insulator on Si substrate including a substrate including silicon and an insulating layer on a surface of the substrate. The thin-film piezoelectric material element includes a thin-film laminated part on a top surface of the insulating layer. The thin-film laminated part includes a YZ seed layer including yttrium and zirconium, and formed on the top surface; a lower electrode film laminated on the YZ seed layer; a piezoelectric material film including lead zirconate titanate, shown by a formula Pb (Zr.sub.xTi.sub.(1-x)) O.sub.3(0≤×≤1), and an upper electrode film laminated on the piezoelectric material film. The thin-film laminated part further includes an upper piezoelectric-material protective-film, laminated on the upper side of the upper electrode film.

Activity of piezoelectric material dimension and electrical properties can be changed with an applied stress. These variations are translated to a change in capacitance of the structure. Use of capacitance-voltage measurements for the extraction of double piezoelectric thin film material deposited at the two faces of a flexible steel sheet is described. Piezoelectric thin film materials are deposited using RF sputtering techniques. Gamry analyzer references 3000 is used to collect the capacitance-voltage measurements from both layers. A developed algorithm extracts directly the piezoelectric coefficients knowing film thickness, applied voltage, and capacitance ratio. The capacitance ratio is the ratio between the capacitances of the film when the applied field in antiparallel and parallel to the poling field direction, respectively. Piezoelectric bulk ceramic is used for calibration and validation by comparing the result with the reported values from literature. Extracted values using the current approach match well values extracted by existing methods.

A sensor includes a plurality of piezoresistive elements and a plurality of electrical connection terminals. The plurality of piezoresistive elements are fabricated on a first side of a substrate. A second side of the substrate is configured to be coupled to an object where a physical disturbance is to be detected. A plurality of electrical connection terminals are coupled to the first side of the substrate.

Disclosed is a method for manufacturing a piezoelectric Al.sub.xGa.sub.1-xN (0.5≤x≤1) thin film, comprising: forming a stress control layer comprised of a Group III nitride on a silicon substrate by chemical vapor deposition (CVD); and depositing a piezoelectric Al.sub.xGa.sub.1-xN (0.5≤x≤1) thin film on the stress control layer, the thin film being deposited by PVD at 0.3 Tm (Tm is melting temperature of a piezoelectric thin film material) or higher. Further, a method for manufacturing a device in conjunction with piezoelectric Al.sub.xGa.sub.1-xN (0.5≤x≤1) thin films is provided.

Activity of piezoelectric material dimension and electrical properties can be changed with an applied stress. These variations are translated to a change in capacitance of the structure. Use of capacitance-voltage measurements for the extraction of double piezoelectric thin film material deposited at the two faces of a flexible steel sheet is described. Piezoelectric thin film materials are deposited using RF sputtering techniques. Gamry analyzer references 3000 is used to collect the capacitance-voltage measurements from both layers. A developed algorithm extracts directly the piezoelectric coefficients knowing film thickness, applied voltage, and capacitance ratio. The capacitance ratio is the ratio between the capacitances of the film when the applied field in antiparallel and parallel to the poling field direction, respectively. Piezoelectric bulk ceramic is used for calibration and validation by comparing the result with the reported values from literature. Extracted values using the current approach match well values extracted by existing methods.

A method for adjusting the stress state of a piezoelectric film having a first stress state at room temperature includes a step of forming an assembly including a carrier having a thermal expansion coefficient, a compliant layer placed on the carrier, and the piezoelectric film placed on the compliant layer, the piezoelectric film having a thermal expansion coefficient different from that of the carrier. The method also includes a step of heat treating the assembly, in which the assembly is heated to a treatment temperature above the glass transition temperature of the compliant layer. The present disclosure also relates to a process for fabricating an acoustic wave device comprising the piezoelectric layer the stress state of which was adjusted as described herein.

A physical disturbance sensor includes a plurality of piezoresistive elements configured in a resistive bridge configuration. A signal transmitter is electrically connected to the physical disturbance sensor and configured to send an encoded signal to the piezoresistive elements of the resistive bridge configuration. A signal receiver is electrically connected to the piezoresistive elements and configured to receive a signal from the physical disturbance sensor. The received signal from the physical disturbance sensor is correlated with the sent encoded signal in determining a measure of physical disturbance.

A substrate having a surface coated with a piezoelectric coating I, the coating including A-xMexN, wherein A is at least one of B, Al, Ga, In, Tl, and Me is at least one metallic element Me from the transition metal groups 3b, 4b, 5b 6b the lanthanides, and Mg the coating I having a thickness d, and further including a transition layer wherein the ratio of atomic percentage of Me to atomic percentage of Al steadily rises along a thickness extent δ3 of said coating for which there is valid:

δ3≤d.

A method for fabricating an array of front ends for an array of packaged electronic components that each comprise: an electrical element packaged within a package comprising a front part of a package comprising an inner section with a cavity therein opposite the resonator defined by the raised frame and an outer section sealing said cavity; and a back part of the package comprising a back cavity in an inner back section, and an outer back section sealing the cavity, said back package further comprising a first and a second via through the back end around said at least one back cavity for coupling to front and back electrodes of the electronic component; the vias terminating in external contact pads that are coupleable in a ‘flip chip’ configuration to a circuit board; the method comprising the stages of: i. Obtaining a carrier substrate having an active membrane layer attached thereto by its rear surface, with a front electrode on the front surface of the active membrane layer; ii. Obtaining an inner front end section; iii. Attaching the inner front end section to the exposed front surface of the front electrode; iv. Detaching the carrier substrate from the rear surface of the active membrane layer; v. Optionally thinning the inner front section; vi. Processing the rear surface by removing material to create an array of at least one island of active membrane on at least one island of front electrode; vii. Creating an array of at least one front cavity by selectively removing at least outer layer of the inner front end section, such that there is one cavity opposite each island of membrane on the front side of the front electrode on the opposite side to the island of active membrane; viii. Applying an outer front end section to the inner front end section and bonding the outer front end section to an outer surface of the inner front end section such that the outer front end section spans across and seals the at least one cavity of the array of front cavities.

A method of forming a piezoelectric thin film can be provided by heating a substrate in a process chamber to a temperature between about 350 degrees Centigrade and about 850 degrees Centigrade to provide a sputtering temperature of the substrate and sputtering a Group III element from a target in the process chamber onto the substrate at the sputtering temperature to provide the piezoelectric thin film including a nitride of the Group III element on the substrate to have a crystallinity of less than about 1.0 degree at Full Width Half Maximum (FWHM) to about 10 arcseconds at FWHM measured using X-ray diffraction (XRD).