Method for forming Semiconductor structures is provided. Method includes forming a fin structure protruding from a front side of a substrate, and the fin structure comprises first semiconductor material layers and second semiconductor material layers alternately stacked. The method includes forming an isolation structure surrounding the fin structure, and forming an epitaxial structure over the fin structure. The method includes forming a first dielectric layer over the epitaxial structure, and forming an S/D structure over the first dielectric layer. The method includes removing the epitaxial structure from a back side of the substrate to form a trench exposing the S/D structure. The method includes forming a first conductive material in the trench, removing a portion of the first conductive material, forming a second conductive material over the first conductive material, and the first conductive material and the second conductive material are made of different materials.

A semiconductor device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer of the semiconductor device includes a standard-gate field-effect transistor. The second semiconductor layer of the semiconductor device includes an extended-gate field-effect transistor. The first semiconductor layer and the second semiconductor layer are formed on top of one another.

A semiconductor device may include a substrate, a lower power line in a lower portion of the substrate, metal layers on the substrate, and a protection structure that is electrically connected to the lower power line and the metal layers. The protection structure may include a doping pattern in the substrate, and a first source/drain pattern that is on the substrate and is electrically connected to an upper portion of the doping pattern. The doping pattern and the first source/drain pattern may include different dopants from each other.

A semiconductor structure includes a stack of channel layers, a source/drain feature connected to the stack of channel layers, a gate structure wrapping around the stack of channel layers, a dielectric liner disposed on a bottom surface of the gate structure, and a source/drain contact underlying the source/drain feature and the stack of channel layers and landing on the dielectric liner. The source/drain contact is electrically connected to the source/drain feature.

A semiconductor device is provided. The semiconductor device includes a backside power distribution (BSPDN), a high thermal conductivity dielectric layer, a heat sink, and a heat transfer pillar. The heat transfer pillar is connected to the high thermal conductivity dielectric layer and extends to the heat sink.

A chip includes one or more first channels extending in a first direction, a first epitaxial (epi) layer coupled to the one or more first channels, one or more second channels extending in the first direction, a second epi layer coupled to the one or more second channels, and a dielectric wall disposed between the first epi layer and the second epi layer.

A microelectronic structure that includes a stacked FET that includes a frontside source/drain and a backside source/drain. A connection via that passes through the backside source/drain. The connection via extends from a frontside surface of the backside source/drain to a backside surface of the backside source/drain. The backside source/drain surrounds the connection via as it passes through the backside source/drain.

Isolation breaks between logic cells in integrated circuit (IC) devices. A source-drain trench between adjacent channel regions includes a pair of source or drain semiconductor bodies, a first of the source or drain bodies in the source-drain trench is connected to a first of the channel regions, a second of the source or drain bodies in the source-drain trench is connected to a second of the channel regions, and a dielectric isolation is in the source-drain trench and between the pair of source or drain bodies. The dielectric isolation may include a void between layers or sidewalls of dielectric. The pair of source or drain bodies may include highly conductive, metallized layers in contact with the dielectric isolation.

A semiconductor structure includes a dielectric layer, a backside contact feature embedded in the dielectric layer, a semiconductor layer disposed over the dielectric layer, a first source/drain feature disposed on a top surface of the backside contact feature and adjacent to the semiconductor layer, a second source/drain feature disposed over the semiconductor layer, a channel member disposed between the first source/drain feature and the second source/drain feature, and a gate structure disposed over the channel member.

A method includes forming a first transistor and a second transistor over a semiconductor substrate, wherein the first transistor and the second transistor are vertically stacked. The method further includes exposing a backside of a first gate stack of the first transistor; forming a backside gate etch stop layer (ESL) on the backside of the first gate stack; patterning a contact opening through the backside gate ESL to expose the first gate stack; and forming a backside gate contact in the contact opening. The backside gate contact extends through the backside gate ESL to electrically connect to the first gate stack.