Provided are a ferroelectric material and an electronic device including same, the ferroelectric material including: a first domain including a first polarization layer which is polarized in a first direction and a first spacer layer disposed adjacent to the first polarization layer; a second domain including a second polarization layer which is polarized in a second direction distinct from the first direction and a second spacer layer disposed adjacent to the second polarization layer; and a structural layer, which is disposed at a domain wall between the first domain and the second domain, and belongs to/has atoms arranged according to a Pbcn space group.

A semiconductor device includes a lower interlayer insulating layer, an active pattern spaced, a plurality of nanosheets, a gate electrode, a source/drain region, a liner layer, a contact isolation layer, and a source/drain contact, where the sidewall of the contact isolation layer includes a first sidewall in contact with the source/drain contact in the first horizontal direction, a second sidewall in contact with each of the liner layer and the active pattern in the first horizontal direction, and a vertex between the first sidewall and the second sidewall, and where a slope profile of the first sidewall of the contact isolation layer and a slope profile of the second sidewall of the contact isolation layer are different.

A semiconductor device structure is provided. The semiconductor device structure includes a source/drain (S/D) feature disposed over a substrate between two adjacent semiconductor layers, a supporting layer disposed between the S/D feature and the substrate, the supporting layer having a curved top surface, a dielectric spacer disposed between and in contact with one of the semiconductor layers and the substrate, wherein the dielectric spacer, the substrate, the supporting layer, and a bottom surface of the S/D feature define an air gap therein.

Methods of forming and a semiconductor devices where the channel region includes a germanium-comprising layer; and a crystalline silicon layer on the germanium-comprising layer. A gate structure over a first surface and a second surface, the second surface opposing the first surface. In some implementations, the crystalline silicon layer can mitigate damage during processing.

A semiconductor device structure is provided. The semiconductor device structure includes a source/drain (S/D) feature disposed over a substrate and between two adjacent semiconductor layers, an inner spacer disposed between and in contact with one of the semiconductor layers and the substrate, and a dielectric layer structure disposed between the S/D feature and the substrate, the dielectric layer structure comprising a first dielectric layer in contact with the inner spacer and the substrate, and a second dielectric layer nested within the first dielectric layer, wherein a bottom surface and sidewall surfaces of the second dielectric layer are in contact with the first dielectric layer, and a bottom surface of the S/D feature, the first dielectric layer, the second dielectric layer, and the inner spacer define an air gap therebetween.

An exemplary gate stack includes a gate dielectric (e.g., a high-k dielectric layer over an interfacial layer) and a gate electrode (e.g., a work function layer over the high-k dielectric layer, a cap over the work function layer, and a bulk fill layer over the cap). The gate stack wraps and/or surrounds a first semiconductor layer disposed over a second semiconductor layer. The gate dielectric and the work function layer (and not the cap and/or the bulk fill layer) fill a space between the first semiconductor layer and the second semiconductor layer. A ratio of oxygen in outer portions of the gate stack to inner portions of the gate stack may be about 1 to about 1.25. A thickness of the work function layer at inner portions of the gate stack may be less than a thickness of the work function layer at outer portions of the gate stack.

An exemplary method for forming a gate stack of a multigate device includes forming a gate dielectric over a channel layer and forming a gate electrode over the gate dielectric. Forming the gate electrode includes forming a work function layer over the gate dielectric and forming a cap over the work function layer. Forming the cap includes forming a metal nitride layer over the work function layer and forming a silicon-comprising layer over the metal nitride layer. Forming the gate electrode includes forming a fluorine-free tungsten layer over the silicon-comprising layer of the cap without breaking vacuum. Forming the fluorine-free tungsten layer over the silicon-comprising layer includes co-flowing a tungsten-comprising precursor (e.g., WCl.sub.5) and a hydrogen-comprising precursor (e.g., H.sub.2).

A semiconductor structure according to the present disclosure includes a substrate, a first source/drain feature and a second source/drain feature disposed over the substrate, and a plurality of nanostructures extending between the first source/drain feature and the second source/drain feature. Each of the first source/drain feature and the second source/drain feature includes a first epitaxial layer in contact with sidewalls of the plurality of nanostructures and a second epitaxial layer spaced apart from the sidewalls of the plurality of nanostructures by the first epitaxial layer. The first epitaxial layer includes a semiconductor material doped with carbon (C) and boron (B).

In one embodiment, a complementary field effect transistor (CFET) device includes one or more metallization layers between stacked transistors.

Methods of forming a metal gate structure of a stacked multi-gate device are provided. A method according to the present disclosure includes depositing a titanium nitride (TiN) layer over a channel region that includes bottom channel layers and top channel layers, depositing a dummy fill layer to cover sidewalls of the bottom channel layers, after the depositing of the dummy fill layer, selectively forming a blocking layer over the TiN layer along sidewalls of the top channel layers, selectively removing the dummy fill layer to release the bottom channel layers, selectively depositing a first work function metal layer to wrap around each of the bottom channel layers, forming a gate isolation layer over a top surface of the first work function metal layer, removing the blocking layer, releasing the top channel layers, and selectively depositing a second work function metal layer to wrap around each of the top channel layers.