A method of forming a semiconductor device includes the following steps. A metal layer with at least one silicon-containing pattern therein is provided. The metal layer is cleaned with a first solution, wherein the first solution comprises a base and a first oxidant. The metal layer is removed with a second solution, wherein the second solution comprises an acid and a second oxidant.

A semiconductor structure includes a fin extending from a substrate and oriented lengthwise in a first direction, where the fin includes a stack of semiconductor layers, an isolation feature disposed over the substrate and oriented lengthwise in a second direction perpendicular to the first direction, where the isolation feature is disposed adjacent to the fin, and a metal gate structure having a top portion disposed over the stack of semiconductor layers and a bottom portion interleaved with the stack of semiconductor layers. Furthermore, a sidewall of the bottom portion of the metal gate structure is defined by a sidewall of the isolation feature, and the top portion of the metal gate structure laterally extends over a top surface of the isolation feature.

A semiconductor device includes a lower interlayer insulating layer, a first plurality of bottom nanosheets, a first plurality of upper nanosheets, an upper isolation layer between the first plurality of bottom nanosheets and the first plurality of upper nanosheets, a first bottom gate electrode on the lower interlayer insulating layer, a first upper gate electrode on an upper surface of the first bottom gate electrode, and a first active cut that extends into each of the first bottom gate electrode and the first plurality of bottom nanosheets in the vertical direction and is on an upper surface of the lower interlayer insulating layer, where the first active cut is spaced apart from the first upper gate electrode in the vertical direction, and where the first active cut at least partially overlaps each of the first upper gate electrode and the first plurality of upper nanosheets in the vertical direction.

Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes forming a first and a second fin-shaped active region over a substrate, the first and second fin-shaped active regions extending lengthwise along a first direction, forming a gate structure over channel regions of the first and second fin-shaped active regions, the gate structure extending lengthwise along a second direction substantially perpendicular to the first direction, forming a trench to separate the gate structure into two segments, the trench extending lengthwise along the first direction and being disposed between the first and second fin-shaped active regions, performing an etching process to enlarge an upper portion of the trench, and forming a gate isolation structure in the trench, and, in a cross-sectional view cut through both the first and second fin-shaped active regions and the gate structure, the gate isolation structure is a T-shape structure.

A method includes forming a fin protruding from a substrate, forming a gate structure across the fin, forming an epitaxial feature over the fin, depositing a dielectric layer covering the epitaxial feature and over sidewalls of the gate structure, performing an etching process to form a trench, the trench dividing the gate structure into first and second gate segments and extending into a region of the dielectric layer, forming a dielectric feature in the trench, recessing a portion of the dielectric feature located in the region, selectively etching the dielectric layer to expose the epitaxial feature, and depositing a conductive feature in physical contact with the epitaxial feature and directly above the portion of the dielectric feature.

A semiconductor device includes a lower interlayer insulating layer and an active pattern thereon, wherein the active pattern extends in a first horizontal direction and is spaced apart from an upper surface of the lower interlayer insulating layer in a vertical direction; first nanosheets on the active pattern; second nanosheets spaced apart from the first nanosheets in the first horizontal direction on the active pattern; a first gate electrode extending in a second horizontal direction and extending around the first plurality of nanosheets; a capping layer on the first gate electrode; and an active cut on the lower interlayer insulating layer, wherein the active cut is spaced apart from the first gate electrode in the first horizontal direction, and an uppermost surface of the active cut is farther than an upper surface of the capping layer from the upper surface of the lower interlayer insulating layer.

An IC structure and a method of forming the same are provided. In an embodiment, an exemplary method of forming the IC structure forming a high-k metal gate structure extending lengthwise along a first direction, forming a trench to separate the high-k metal gate structure into two portions, conformally depositing a first dielectric layer to substantially fill the trench, after the conformally depositing of the first dielectric layer, forming a patterned mask over the high-k metal gate structure, the patterned mask comprising an opening disposed directly over the trench, etching back the first dielectric layer while using the patterned mask as an etch mask to obtain a thinned first dielectric layer, and after the etching of the first dielectric layer, forming a second dielectric layer in the trench and on the thinned first dielectric layer.

Embodiments of the invention are directed to a method of fabricating an integrated circuit (IC). The method includes performing fabrication operations to form transistors on a substrate. The fabrication operations include forming a sacrificial metal gate and forming a shared non-sacrificial metal gate. The sacrificial metal gate is recessed to form a sacrificial metal gate, and the shared non-sacrificial metal gate is recessed to form a recessed shared non-sacrificial metal gate. A pattern is formed over the sacrificial metal gate and the recessed shared non-sacrificial metal gate. The pattern defines a single diffusion break footprint over a top surface of the sacrificial metal gate, along with a gate-cut footprint over a central region of a top surface of the recessed shared non-sacrificial metal gate.

A semiconductor device includes a substrate, a lower channel stack on the substrate, an upper channel stack on the lower channel stack, a gate electrode extending around the lower channel stack and the upper channel stack, a gate cut region that is on the substrate and includes an insulating material, a semiconductor material layer between the upper channel stack and the gate cut region, and an insulating layer that is between the semiconductor material layer and the upper channel stack.

Techniques are provided herein to form semiconductor devices having self-aligned gate cut structures. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut structure that includes a dielectric material interrupts the gate structure between the neighboring semiconductor devices. Due to the process of forming the gate cut structure, the distance between the gate cut structure and the semiconductor region of one of the neighboring semiconductor devices is substantially the same as (e.g., within 1.5 nm of) the distance between the gate cut structure and the semiconductor region of the other one of the neighboring semiconductor devices and the gate cut structure extends beyond the width of the gate structure to also interrupt gate spacers on the sidewalls of the gate structure.