Techniques are provided herein to form semiconductor devices having conductive backside structures to couple various transistor structures. In some embodiments, a given conductive backside structure acts as a shunt interconnect between two transistors, such as between the gate of one transistor and the source or drain region of another transistor. In an example, an integrated circuit includes two transistor devices having semiconductor material extending between separate source and drain regions and different gate structures over or around the semiconductor material of the two transistor devices. A conductive backside structure may be formed from the backside of the integrated circuit (e.g., after removing all or most of the substrate), where the backside structure contacts the source or drain region of one transistor and the gate structure of the other transistor.

A device includes a semiconductor fin, a gate structure, gate spacers, and a dielectric feature. The semiconductor fin is over a substrate. The gate structure is over the semiconductor fin and includes a gate dielectric layer over the semiconductor fin and a gate metal covering the gate dielectric layer. The gate spacers are on opposite sides of the gate structure. The dielectric feature is over the substrate. The dielectric feature is in contact with the gate metal, the gate dielectric layer, and the gate spacers, and an interface between the gate metal and the dielectric feature is substantially aligned with an interface between the dielectric feature and one of the gate spacers.

A semiconductor device includes active patterns spaced apart from one another in a first direction and extending in a second direction different from the first direction; a lower channel pattern and a lower source/drain pattern on the active patterns, in which the lower channel pattern and the lower source/drain pattern are alternately arranged in the second direction; an upper channel pattern on the lower channel pattern, and an upper source/drain pattern on the lower source/drain pattern; a gate pattern on the active patterns and on the lower channel pattern and the upper channel pattern; and a gate inner spacer on the gate pattern, and between the lower source/drain pattern and the upper source/drain pattern.

A semiconductor structure includes a semiconductor fin protruding from a substrate and extending across the substrate along a first lateral direction. The semiconductor structure includes a plurality of gate structures disposed over the substrate, where each gate structure extends along a second lateral direction perpendicular to the first lateral direction. The semiconductor structure includes a gate isolation structure disposed over the gate structures. The gate isolation structure including a first portion and a second portion connected to the first portion. The first portion extends over the gate structures along the first lateral direction. The second portion partially extends into the semiconductor fin along the second lateral direction.

An integrated circuit device may include at least one first semiconductor pattern extending in a first horizontal direction, a first source/drain region connected to an end of the at least one first semiconductor pattern in the first horizontal direction, at least one second semiconductor pattern extending in the first horizontal direction and spaced apart from the at least one first semiconductor pattern in a second horizontal direction, a second source/drain region connected to an end of the at least one second semiconductor pattern in the first horizontal direction, and an insulating wall in an insulating wall opening that extends in the first horizontal direction, between the at least one first semiconductor pattern and the at least one second semiconductor pattern and between the first source/drain region and the second source/drain region.

A semiconductor device includes a lower interlayer insulating layer, an insulating pattern extending in a first direction on the lower interlayer insulating layer, a plurality of nanosheets on the insulating pattern and spaced apart in a third direction, an active cut penetrating the lower interlayer insulating layer, the insulating pattern and the plurality of nanosheets, the active cut extending in a second direction and comprising an upper surface extending between opposing first and second sidewalls, and a first gate electrode extending in the second direction on the insulating pattern, wherein the first gate electrode includes a first portion in contact with the first sidewall of the active cut in the second direction, a second portion in contact with the upper surface of the active cut, and a third portion in contact with the second sidewall of the active cut, where the second connects the first portion and the third portion.

A semiconductor device includes a substrate, a substrate insulating layer, a first isolation region, gate electrodes, a plurality of channel layers, source/drain regions, a backside contact plug, and a backside isolation region. The substrate includes a first region and a second region. The substrate insulating layer is disposed on a lower surface of the substrate. The first isolation region passes through the substrate and extends towards the substrate insulating layer. The gate electrodes are disposed on an upper surface of the substrate. The plurality of channel layers are surrounded by the gate electrodes. The source/drain regions are disposed at opposite sides of the gate electrodes, and are connected to the plurality of channel layers. The backside contact plug is connected to the source/drain regions. The backside isolation region passes through the substrate and the substrate insulating layer, and the backside isolation region separates the substrate.

A semiconductor device is provided. The semiconductor device includes an active pattern extending along a first horizontal direction on an upper surface of a substrate, first nanosheets spaced apart from each other along a vertical direction on the active pattern, a first gate electrode extending along a second horizontal direction on the active pattern, an active cut spaced apart from the first gate electrode in the first horizontal direction, a bottom surface of the active cut formed lower than a bottom surface of the gate electrode, a source/drain region between the first gate electrode and the active cut on the active pattern, and a source/drain contact on an upper surface of the source/drain region. The source/drain contact is electrically connected to the source/drain region, and an uppermost surface of the source/drain contact is formed lower than an upper surface of the active cut.

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate along a first direction, and a plurality of second nanostructures formed adjacent to the first nanostructures. The semiconductor structure includes a first gate structure formed on the first nanostructures along a second direction, and the first gate structure includes a first gate dielectric layer. The semiconductor structure includes a second gate structure formed on the second nanostructures. The semiconductor structure includes a dielectric wall structure between the first gate structure and the second gate structure along the first direction. The dielectric wall structure has a top portion and a bottom portion, and the bottom portion is wider than the top portion.

A stacked integrated circuit device includes a plurality of nanosheet stack structures, a gate separator, a lower gate electrode, an upper gate electrode, a lower gate cut structure, an upper gate cut structure, and a coupling gate cut structure. The upper gate electrode extends along a side surface of the coupling gate cut structure and is electrically connected to the lower gate electrode.