An integrated circuit and a formation method thereof are provided. The integrated circuit includes: an active structure, formed on a semiconductor substrate, and extending along a first lateral direction; first and second gate lines, extending along a second lateral direction on the semiconductor substrate, and crossing the active structure; an isolation wall, extending along the second lateral direction between the first and second gate lines, and cutting through the active structure; a first source/drain contact, extending along the second lateral direction between the first gate line and the isolation wall, and crossing the active structure; and a first source/drain via, disposed on the first source/drain contact, and laterally extending along the first direction to overlap the isolation wall.

Embodiments with present disclosure provides a gate-all-around FET device including extended bottom inner spacers. The extended bottom inner prevents the subsequently formed epitaxial source/drain region from volume loss and induces compressive strain in the channel region to prevent strain loss and channel resistance degradation.

A microelectronic structure that includes a stacked nanosheet FET transistor that includes an upper nanosheet transistor and a lower nanosheet transistor. The upper nanosheet transistor includes an upper source/drain and the upper source/drain includes an upper tip that is pointed in a first direction. The lower nanosheet transistor includes a lower source/drain and the lower source/drain includes a lower tip pointed in a second direction. The first direction is different than the second direction.

A semiconductor structure includes a plurality of gate-all-around field effect transistors, each of the gate-all-around field effect transistors including: first and second source-drain regions; a plurality of nanowire channels interconnecting the first and second source-drain regions; and a common gate. The common gate includes an upper gate portion above the plurality of nanowire channels and a lower gate portion surrounding the plurality of nanowire channels. A unitary spacer structure includes an upper spacer portion between the upper gate portion and the first and second source-drain regions and a lower spacer portion between the lower gate portion and first and second source-drain regions. The upper spacer portion and the lower spacer portion have aligned left and right edges.

A semiconductor device includes a first transistor, a second transistor and an interconnect structure. The interconnect structure is disposed over the first transistor and the second transistor, wherein the interconnect structure includes a first conductive via electrically connecting a first source/drain contact of the first transistor to a second gate structure of the second transistor. The first conductive via is in contact with a top surface of the first source/drain contact and a side surface of the first source/drain contact.

A semiconductor die and the method of forming the same are provided. The semiconductor die includes a first interconnect structure, a second interconnect structure including a conductive feature, and a device layer between the first interconnect structure and the second interconnect structure. The device layer includes a semiconductor fin, a first gate structure on the semiconductor fin, a source/drain region adjacent the first gate structure, and a shared contact extending through the semiconductor fin to be electrically connected to the source/drain region and the first gate structure. The conductive feature contacts the shared contact.

A semiconductor device fabrication method is provided and includes executing front-end-of-line (FEOL) processing to form first and second source/drain (S/D) epitaxy, forming a middle-of-line (MOL) contact to the first S/D epitaxy, executing a self-aligned backside S/D cut to form an opening in which respective sides of each of the first and second S/D epitaxy are exposed, depositing metallic material along the respective sides of each of the first and second S/D epitaxy in the opening and forming silicide from the metallic material whereby the silicide at the first S/D epitaxy contacts the MOL contact and the sides of the first S/D epitaxy.

A semiconductor device and an isolation structure and a contact etch stop layer thereof are provided. According to an embodiment of the present disclosure, a semiconductor device is provided, which includes a first dielectric layer and a second dielectric layer. The first dielectric layer is deposited on the sidewall of an active device or formed in a trench of a gate structure. The second dielectric layer covers the first dielectric layer, wherein the dielectric constant of the first dielectric layer is between 2 and 2.5, and the dielectric constant of the second dielectric layer is less than or equal to 4. In some embodiments, a dielectric bilayer is composed of amorphous boron nitride and crystalline boron nitride.

A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second nanostructured channel regions disposed on the substrate, a gate structure surrounding the first and second nanostructured channel regions, an inner gate spacer disposed along a sidewall of the gate structure and between the first and second nanostructured channel regions, and a source/drain (S/D) region. The S/D region includes an epitaxial liner disposed along sidewalls of the first and second nanostructured channel regions and the inner gate spacer and a germanium-based epitaxial region disposed on the epitaxial liner. The semiconductor further includes an isolation structure disposed between the germanium-based epitaxial region and the substrate.

Integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.