A method for producing a device comprising GAA transistors. Advantageously, the channels of the transistors are produced by deposition of a semiconductor material, preferably a 2D material, after successive removal of certain layers of the initial stack. The gates-all-around are produced after selective removal of the other layers from the initial stack. The initial stack does not comprise the semiconductor material, nor the material of the gates. The subsequent deposition of the semiconductor material aims to better preserve the semiconductor material.

IC devices with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as angled if a longitudinal axis of an elongated semiconductor structure (e.g., a fin or a nanoribbon) based on which the transistor is built is at an angle other than 0 degrees or 90 degrees with respect to edges of front or back faces of a support structure on/in which the transistor resides, e.g., at an angle between 10 degrees and 80 degrees with respect to at least one of such edges. Angled transistors provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips.

A method of forming an electrical contact in a semiconductor structure includes performing a cavity shaping process on a semiconductor structures having an n-type metal oxide semiconductor (n-MOS) region and/or a p-type MOS (p-MOS) region, the cavity shaping process comprising forming an n-MOS cavity in an exposed surface of the n-MOS region and/or a p-MOS cavity in an exposed surface of the p-MOS region, wherein the cavity shaping process is configured to increase the surface area of the exposed surface of the n-MOS region or the p-MOS region. In some embodiments, the method includes performing a first selective deposition process to form a p-MOS cavity contact, selectively in the p-MOS cavity.

A semiconductor device includes a substrate having an I/O region and a core region; a first transistor in the I/O region; and a second transistor in the core region, wherein the first transistor includes a first gate structure having: an interfacial layer; a first high-k region over the interfacial layer; and a conductive layer over the first high-k region, wherein the second transistor includes a second gate structure having: the interfacial layer; a second high-k region over the interfacial layer; and the conductive layer over the second high-k region, and where in the first high-k region is thicker than the second high-k region.

Design of overlay-based front end defect quick turn test chip is described. In an example, an integrated circuit structure includes a device layer including a vertical stack of horizontal nanowires or a fin, a gate electrode over the vertical stack of horizontal nanowires or the fin, a conductive trench contact adjacent to the gate electrode, and a dielectric sidewall spacer between the gate electrode and the conductive trench contact. The integrated circuit structure also includes a metallization layer immediately above the device layer, the metallization layer including a first test pad and a second test pad.

Voltage contrast (VC) image simulation capability and associated test structures are described. In an example, a circuit structure includes an inter-layer dielectric (ILD) layer. A plurality of unidirectional wires is in the ILD layer. In one specific example, the integrated circuit structure includes one or more additional wires in the ILD layer, the one or more additional wires along a direction different than a direction of the plurality of unidirectional wires, and the one or more additional wires are each continuous with a corresponding one of the plurality of unidirectional wires at a location between ends of the corresponding one of the plurality of unidirectional wires. In another specific example, one or more of the plurality of unidirectional wires have a line width transition therein.

A field effect transistor (FET) structure and method for making the same is disclosed. In an aspect, a method of fabricating a semiconductor structure comprises providing a FET structure disposed above a substrate, the FET structure comprising a vertical metal gate structure disposed between a pair of source/drain (S/D) epitaxial (EPI) structures and having a set of vertically-stacked, horizontal nanosheets extending through the vertical metal gate structure in the first horizontal direction to electrically connect the S/D EPI structures to each other. The method further comprises removing the substrate, removing the portion of vertical metal gate structure below the bottom-most nanosheet, removing at least enough of the bottom-most nanosheet to sever the its electrical conducting path between the S/D EPI structures, and filling the void created by the removed gate metal and nanosheet with a dielectric material that also covers the bottom surfaces of the S/D EPI structures.

A field effect transistor (FET) structure and method for making the same is disclosed. In an aspect, a FET structure comprises a vertical metal gate disposed between a first and second source/drain (S/D) epitaxial (EPI) structure and having a set of vertically-stacked, horizontal channels, all but the top channel connecting the first and second S/D EPI structures through the vertical metal gate. A high-K dielectric material is disposed between the vertical metal gate and each of the horizontal channels, and vertical spacer layers separate the vertical metal gate from the S/D EPI structures. A low-K dielectric structure is disposed above the top-most portion of the vertical metal gate and fills a recess above the vertical metal gate and between the first vertical spacer layer and the second vertical spacer layer.

A device includes a stack of first nanostructures; a first insulating layer adjacent to the stack of first nanostructures; and a first source/drain region over the first insulating layer, wherein the first source/drain region includes: first semiconductor layers, wherein each first semiconductor layer covers a sidewall of a respective first nanostructure, wherein the first semiconductor layers includes a first semiconductor material; second semiconductor layers, wherein each second semiconductor layer covers a sidewall of a respective first semiconductor layer, wherein the second semiconductor layers includes a second semiconductor material different from the first semiconductor material; and a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer is a third semiconductor material different from the first semiconductor material and different from the second semiconductor material.

A capacitor cell includes an active region and a power line supplying VDD. The active region includes nanosheets extending in the X direction as channels of transistors. The power line extends in the X direction on the back side of the transistors and overlaps the active region in planar view. The sources/drains of the transistors in the active region are connected to the power line through vias. VSS is supplied to gate interconnects of the transistors.