Systems, methods, and apparatus are provided for bifurcated access line contacts. Horizontally oriented access devices each have a first source/drain region and a second source drain region separated by channel regions. Gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures separated from channel regions by gate dielectrics. Horizontally oriented storage nodes can be electrically coupled to the second source/drain regions of the horizontally oriented access devices. A staircase structure at each level on a periphery of the array of vertically stacked memory cells and a plurality of separate vertical connections each connected to a different one of a plurality of horizontally oriented access lines formed with the GAA structures on each level of the array.

A method includes receiving a structure including a first region and a second region, forming a dielectric layer over the first region and the second region, forming a first patterned layer of a first dipole material on the dielectric layer in the first region, performing a first thermal drive-in operation to drive the first dipole material into the dielectric layer, forming a second patterned layer of a second dipole material on the dielectric layer in the second region, performing a second thermal drive-in operation to drive the second dipole material into the dielectric layer, performing a thermal operation to adjust distribution of the first dipole material or both the first and the second dipole materials in the dielectric layer, and forming a gate electrode layer over the dielectric layer. A portion of the first region overlaps with the second region.

A method can include receiving a first and a second power supply voltage at terminals disposed at a first side of an IC device. Rows of insulated gate field effect transistors (IGFETs) can be provided as a second side of the IC device. Each IGFET can include first and second source/drains (S/Ds), multiple channels, and a control gate that surrounds the channels. Coupling the first or second power supply voltage from one of the terminals to a first S/D of an IGFET via conductive vias and conductive lines. The conductive vias connected to adjacent conductive lines can be offset from one another in the first direction. Corresponding devices and systems are also disclosed.

A semiconductor device includes channel members vertically stacked, a gate dielectric layer wrapping around each of the channel members, a first work function (WF) layer disposed over the gate dielectric layer and wrapping around each of the channel members, a first WF isolation layer disposed over the first WF layer, a second WF layer disposed over the first WF isolation layer, a second WF isolation layer disposed over the second WF layer, and a metal fill layer disposed over the second WF isolation layer. The first WF layer has a uniform thickness. The second WF isolation layer is a nitride-containing layer.

A semiconductor device is provided. The semiconductor device includes a backside power distribution (BSPDN), a high thermal conductivity dielectric layer, a heat sink, and a heat transfer pillar. The heat transfer pillar is connected to the high thermal conductivity dielectric layer and extends to the heat sink.

Techniques to form semiconductor devices that include forksheet transistors with a self-aligned dielectric spine. In an example, first and second semiconductor devices have first and second semiconductor regions, respectively, extending in a first direction between corresponding source or drain regions. The first and second semiconductor regions may include any number of nanosheets with first and second gate structures extending around three sides of each of the first and second semiconductor regions, respectively. A dielectric spine extends in the first direction directly between the first and second semiconductor regions. In an example, the gate dielectric of each of the first and second gate structures is still present between the first and second semiconductor regions and the dielectric spine. An uppermost width of the dielectric spine may be smaller (e.g., 5 nm or more smaller) than a lower width of the dielectric spine that is between the first and second gate structures.

A semiconductor device includes an active fin protruding from a substrate; a plurality of channel layers on the active fin and spaced apart from each other in a vertical direction; a gate pattern intersecting the active fin and the plurality of channel layers; and source/drain regions on recessed regions of the active fin on both sides of the gate pattern. The gate pattern includes a gate dielectric layer, inner conductive layers, and a conductive liner. The inner conductive layers are disposed between the plurality of channel layers, and between the active fin and a lowermost channel layer among the plurality of channel layers. The conductive liner has a first thickness on an upper surface of an uppermost channel layer in the vertical direction, and at least one of the inner conductive layers have a second thickness in the vertical direction. The first thickness is less than the second thickness.

Methods for fabricating semiconductor structures are provided. An exemplary method includes forming a first transistor structure and a second transistor structure over a substrate, wherein each transistor structure includes at least one nanosheet. The method further includes depositing a metal over each transistor structure and around each nanosheet; depositing a coating over the metal; depositing a mask over the coating; and patterning the mask to define a patterned mask, wherein the patterned mask lies over a masked portion of the coating and the second transistor structure, and wherein the patterned mask does not lie over an unmasked portion of the coating and the first transistor structure. The method further includes etching the unmasked portion of the coating and the metal over the first transistor structure using a dry etching process with a process pressure of from 30 to 60 (mTorr).

The disclosure relates to a complementary field effect transistor, CFET, structure. The CFET structure comprises: a first CFET element which is arranged in a first row of the CFET structure; and a second CFET element which is arranged in a second row of the CFET structure, wherein the second row is arranged laterally offset to the first row; wherein the first and the second CFET element each comprise: a first transistor structure, and a second transistor structure which is arranged above the first transistor structure. The CFET structure further comprises a shared signal routing structure which is arranged between the first and the second CFET element; wherein the shared signal routing structure is electrically connected to the first and/or the second transistor structure of the first and/or of the second CFET element, respectively.

A method for forming a 2D channel field-effect transistor device is provided. The method includes forming a device layer stack on a substrate. The device layer stack includes lower and upper sacrificial layers and a channel layer of a 2D material. The method further includes embedding the device layer stack in a dummy layer, forming a gate cavity in the dummy layer, and removing the sacrificial layers from the device layer stack by etching the sacrificial material from the gate cavity. After removing the sacrificial layers, the method includes forming an oxide liner along sidewalls of the gate cavity including an oxidation process to oxidize a thickness portion of the dummy layer, forming a gate stack in the gate cavity to surround the channel layer, forming source/drain contact cavities in the dummy layer, forming source/drain contacts in the source/drain contact cavities, and replacing the dummy layer with a dielectric layer.