The invention provides an electronic cascode power device. The electronic cascode power device has a high-side terminal, a low-side terminal and a control terminal. The electronic cascode power device comprises: a high-voltage silicon (Si) super-junction MOSFET with a drain connected to the high-side terminal of the cascode device; a low-voltage gallium nitride (GaN) HEMT with a drain connected to a source of the high-voltage Si super-junction MOSFET, a source connected to the low-side terminal of the cascode device and a gate connected to the control terminal of the cascode device; and an overvoltage clamping circuit connected between the drain and source of the low-voltage GaN HEMT. The provided cascode structure can effectively suppress the reverse-recovery process of super-junction MOSFET, achieving nearly 50% reduction in overall switching loss at high current levels.

A power module has a first layer, a second layer, and an inductor assembly. The first layer has a plurality of connecting pillars, a first plurality of capacitors electrically connected in parallel between an input node and a reference ground, and a second plurality of capacitors electrically connected in parallel between an output node and the reference ground. The second layer is attached between the first layer and the inductor assembly, having a first pair of switches forming a first switch node, and a second pair of switches forming a second switch node. The first pair of switches and the second pair of switches are electrically connected between the input node and the reference ground. The inductor assembly has a first inductor electrically connected between the output node and the first switch node and a second inductor electrically connected between the output node and the second switch node.

A semiconductor device includes a support, a first semiconductor element and a second semiconductor element that are disposed on a first side in a thickness direction of the support, and a sealing body covering a part of the support and the first and the second semiconductor elements. The support includes a first surface facing a second side in the thickness direction and exposed from the sealing body, and the first surface includes an uneven region comprising a plurality of dot-shaped recesses overlapping with each other.

According to one embodiment, a semiconductor device includes: a substrate; a case provided on the substrate and including a resin layer and a terminal; and a circuit board provided on the substrate and including a semiconductor chip and a wiring electrically connected to the semiconductor chip and the terminal, wherein the terminal includes a first portion extending from the resin layer toward the circuit board, a second portion bonded to the wiring, and a third portion between the first portion and the second portion, and the third portion is recessed toward an opposite side of a side of the substrate from the second portion.

Methods, systems, and devices for dielectric windows for groups of vias through semiconductor substrates are described. For example, a semiconductor component (e.g., a semiconductor die, a semiconductor wafer) may be formed with one or more dielectric windows through a substrate of the semiconductor component, through which a group of multiple vias may be formed to support signaling with circuitry of the semiconductor component. In some implementations, a set of multiple cavities may be formed through a given dielectric portion and, in each of the multiple cavities, a conductive portion (e.g., one or more conductive materials) may be formed to support multiple electrically isolated contacts. In various examples, such vias may include contacts themselves (e.g., for vias that extend to the surface of the semiconductor component), or may be otherwise coupled with (e.g., contiguous with, electrically coupled with) a contact portion that has a different cross-section than the vias.

Methods, systems, and devices for dielectric windows for groups of vias through semiconductor substrates are described. For example, a semiconductor component (e.g., a semiconductor die, a semiconductor wafer) may be formed with one or more dielectric windows through a substrate of the semiconductor component, through which a group of multiple vias may be formed to support signaling with circuitry of the semiconductor component. In some implementations, a set of multiple cavities may be formed through a given dielectric portion and, in each of the multiple cavities, a conductive portion (e.g., one or more conductive materials) may be formed to support multiple electrically isolated contacts. In various examples, such vias may include contacts themselves (e.g., for vias that extend to the surface of the semiconductor component), or may be otherwise coupled with (e.g., contiguous with, electrically coupled with) a contact portion that has a different cross-section than the vias.

A semiconductor power device, includes: a substrate; a first, a second, a third, and a fourth conductive regions disposed on the substrate, where the first conductive region and the second conductive region are disposed on two opposite sides of the third conductive region, the fourth conductive region is disposed between the first conductive region and the third conductive region and between the second conductive region and the third conductive region, the first, the second, and the fourth conductive regions are configured to transmit DC signals, and the third conductive region is configured to transmit AC signals; a first power chip mounted in the first conductive region and connected to the third conductive region; a second power chip mounted in the second conductive region and connected to the third conductive region; and a third power chip mounted in the third conductive region and connected to the fourth conductive region.

A capacitor structure includes a base substrate, a through via extending in a vertical direction from a top surface of the base substrate to a bottom surface of the base substrate, a first sub-capacitor structure disposed on the bottom surface of the base substrate and including a first lower electrode electrically connected to a first end of the through via, a first upper electrode, and a first capacitor dielectric layer between the first lower electrode and the first upper electrode, and a second sub-capacitor structure disposed on the top surface of the base substrate and including a second lower electrode electrically connected to a second end, opposite to the first end, of the through via, a second upper electrode, and a second capacitor dielectric layer between the second lower electrode and the second upper electrode on the top surface of the base substrate.

Disclosed herein is a semiconductor module that includes a substrate body including first to third insulating layers, and a semiconductor IC having a main surface on which a redistribution layer is provided and a back surface partially covered with a back surface conductor. The semiconductor IC is embedded in the first insulating layer such that the main surface faces the second insulating layer side, and that the back surface faces the third insulating layer side. The thermal expansion coefficient of the redistribution layer is smaller than the thermal expansion coefficient of the back surface conductor. The thermal expansion coefficient of the second insulating layer is larger than the thermal expansion coefficient of the third insulating layer.

A semiconductor device includes a first semiconductor element, a second semiconductor element, a first conductive member, and a second conductive member. The first semiconductor element includes a first drain electrode and a first drain electrode on a first side in a first direction. The second semiconductor element includes a second drain electrode and a second source electrode on the first side in the first direction, and the second semiconductor element is next to the first semiconductor element in a second direction perpendicular to the first direction. The first conductive member is electrically bonded to the first drain electrode and the second drain electrode. The second conductive member is electrically bonded to the first source electrode and the second source electrode. The first conductive member and the second conductive member each intersect a gap between the first semiconductor element and the second semiconductor element as viewed in the first direction.