The disclosure concerns an electronic device provided with two high electron mobility transistors stacked on each other and having in common their source, drain, and gate electrodes. For example, each of these electrodes extends perpendicularly to the two transistors. For example, the source and drain electrodes electrically contact the conduction channels of each of the transistors so that said channels are electrically connected in parallel.

A semiconductor structure including a substrate and a capacitor is provided. The capacitor is located on the substrate. The capacitor includes a first electrode, a second electrode, a first dielectric layer, and a second dielectric layer. The first electrode is located on the substrate. The first electrode has a first surface and a second surface opposite to each other. The second electrode is located on the first electrode. The first dielectric layer is located between the first surface and the second electrode. The second dielectric layer is located between the first dielectric layer and the second electrode and between the second surface and the second electrode.

A semiconductor device includes a first semiconductor element, a plurality of leads, a plurality of wires and a sealing resin covering the first semiconductor element, the plurality of wires, and at least a part of each of the plurality of leads. The plurality of leads include a first lead. The plurality of wires include a plurality of first wires each having a first bonding portion connected to the first semiconductor element and a second bonding portion connected to the first lead. The first lead includes a first portion extending in an x first direction. The second bonding portions of the plurality of first wires are connected to the first portion and arranged in a plurality of rows along the x direction.

A power module having a first integrated power board having a first positive terminal, a first power semiconductor die, a first middle point terminal, a second power semiconductor die and a first negative terminal, a second integrated power board having a second positive terminal, another first power semiconductor die, a second middle point terminal, another second power semiconductor die and a second negative terminal, a PCB busbar having opposite first face and second face and having power conductive tracks and connection pads, on both said first face and said second face, wherein said first integrated power board has its first positive terminal, first middle point terminal and first negative terminal connected to connection pads on said first face, wherein said second integrated power board has its first positive terminal, first middle point terminal and first negative terminal connected to further connection pads on said second face.

A semiconductor power device is described, having: a package; a power die arranged within the package and integrating a power structure that generates a load electric current designed to be supplied to an electric load. The device is also provided, within the package, with: at least a first conductive path designed to be flown through by a first sensing current, which is a function of the load electric current; and a current sensor with magnetic-based operation, integrated into a sensor die coupled to the first conductive path and which generates a current sensing signal on the basis of the first sensing current and indicative of the load electric current.

A first surface shape of a module base and a second surface shape of a heatsink base are fitted to each other, and thus the module base and the heatsink base are fixed to each other. One of the first surface shape and the second surface shape includes a first protrusion and a second protrusion, and the other includes a first recess fitted to the first protrusion and a second recess fitted to the second protrusion. The first protrusion has a tip end in contact with the first recess, and the second protrusion has a tip end away from the second recess.

A first surface shape of a module base and a second surface shape of a heatsink base are fitted to each other, and thus the module base and the heatsink base are fixed to each other. One of the first surface shape and the second surface shape includes a first protrusion and a second protrusion, and the other includes a first recess fitted to the first protrusion and a second recess fitted to the second protrusion. The first protrusion has a tip end in contact with the first recess, and the second protrusion has a tip end away from the second recess.

A semiconductor device includes a plurality of transistors electrically connected in parallel to each other, each of the plurality of transistors including a first pad; and a conductive member. The first pad is a source pad or an emitter pad. The first pad includes a first connection region; and a second connection region and a third connection region, the first connection region being located between the second connection region and the third connection region. The semiconductor device includes a first connection member that connects the first connection region to the conductive member; a second connection member that connects second connection regions of two transistors among the plurality of transistors; and a third connection member that connects third connection regions of the two transistors among the plurality of transistors.

An inverter device includes: an interconnect substrate having a first interconnect layer and a second interconnect layer; and a plurality of transistors arranged in a middle layer, each having a source region and a drain region surrounding the source region on one face. The plurality of transistors include a first transistor placed with the one face facing the first interconnect layer and having a drain connected to a first interconnect in the first interconnect layer and a source connected to a second interconnect in the first interconnect layer. The first interconnect overlaps the drain region of the first transistor in planar view, and the second interconnect extends from the opening of the first interconnect to the position overlapping the source region of the first transistor in planar view.

A semiconductor module includes first to fourth semiconductor elements, a plurality of wiring patterns, a first power source terminal, second power source terminals, a first intermediate point terminal and a second intermediate point terminal, and a full bridge circuit is formed in the semiconductor module. The semiconductor module further includes a temperature detection element; first and second temperature detection wiring patterns; and first and second temperature detection terminals. The temperature detection element is disposed in a region surrounded by a first switching path and a second switching path. The semiconductor module is configured to reduce noises caused by a parasitic capacitance between a second wiring pattern and a first temperature detection wiring pattern, and a parasitic capacitance between a fourth wiring pattern and a first temperature detection wiring pattern.