A first electrode includes an elongated first contact surface. A second electrode includes the second contact surface provided to face the first contact surface and extend in parallel to the first contact surface. An insulating material is provided between the first electrode and the second electrode. The insulating material extends between the first contact surface and the second contact surface, and has contact with the first contact surface and the second contact surface. The first electrode includes a first corner part located in an end portion of the first contact surface in a width direction. The second electrode includes a second corner part located in an end portion of the second contact surface in a width direction. Each of the first corner part and the second corner part includes any one of a chamfered part and a burr part.

A first electrode includes an elongated first contact surface. A second electrode includes the second contact surface provided to face the first contact surface and extend in parallel to the first contact surface. An insulating material is provided between the first electrode and the second electrode. The insulating material extends between the first contact surface and the second contact surface, and has contact with the first contact surface and the second contact surface. The first electrode includes a first corner part located in an end portion of the first contact surface in a width direction. The second electrode includes a second corner part located in an end portion of the second contact surface in a width direction. Each of the first corner part and the second corner part includes any one of a chamfered part and a burr part.

An embodiment includes a method for floorplanning of a circuit region of an IC device which includes: obtaining a floorplan for the circuit region; determining a location of an in-die stitching boundary for the floorplan, the in-die stitching boundary extending in a first direction across the floorplan; placing one or more rows of filler cells in an in-die stitching sub-region of the floorplan, wherein the one or more rows of filler cells extend in the first direction and the in-die stitching sub-region extends along the in-die stitching boundary; and placing in each of a first and a second sub-region of the floorplan on opposite sides of the in-die stitching sub-region, circuit cells in a plurality of rows extending in parallel in the first direction, wherein the filler cells have a critical dimension which is greater than a corresponding critical dimension of the circuit cells of the first and second sub-regions.

The disclosure provides a method for fabricating a low resistance contact on a semiconductor substrate comprising a metal oxide semiconductor (MOS) device. The method comprises fabricating a via to a source or drain region of the MOS device, providing an insulating layer along a sidewall of the via while maintaining or reestablishing the exposed source or drain region, using ion implantation to implant a metallic element into the exposed source or drain region of the semiconductor substrate through the via to form an implanted layer, annealing the implanted layer to form a silicide layer comprising silicon and the metallic element on the source or drain region of the MOS device, and depositing a low resistance metal in the via to form the low resistance contact on the semiconductor substrate comprising the MOS device. The disclosure also provides a device comprising a low resistance contact fabricated by said method.

A semiconductor device comprises a first conductive layer, a first semiconductor element bonded to one side in a first direction of the first conductive layer, a first power terminal conductive to the first conductive layer and the first semiconductor element, a first sealing resin covering the first conductive layer and the first semiconductor element, and a first extension terminal conductively bonded to the first power terminal. The first power terminal has a first exposed portion exposed from the first sealing resin. The first extension terminal is conductively bonded to the first exposed portion.

The present disclosure discloses a package including a first support portion, a second support portion, and multiple pins. The first support portion includes a first upper metal layer and a first lower metal layer, wherein the first lower metal layer is connected to and overlaps with the first upper metal layer, corresponding to the position of the first upper metal layer. The second support portion is laterally separated from the first support portion, and the second support portion includes a second metal layer. The multiple pins are laterally separated from the first support portion and the second support portion, where in a top view, a ratio of a maximum length of the second metal layer to a maximum length of the package is greater than .

A semiconductor chip package includes a semiconductor transistor chip having a first side and a second side opposite the first side. The first side includes first load current chip pads and second load current chip pads. An interconnect substrate includes a first metal layer, a second metal layer, and an insulating material disposed between the first metal layer and the second metal layer. The first metal layer includes a pattern of holes, the second metal layer includes a pattern of protrusions, and the protrusions pass through the holes. The semiconductor transistor chip is mounted on the interconnect substrate with the first side facing the interconnect substrate. The first metal layer is connected to a plurality of the first load current chip pads and the second metal layer is connected via the pattern of protrusions to a plurality of the second load current chip pads.

A semiconductor chip package includes a semiconductor transistor chip having a first side and a second side opposite the first side. The first side includes first load current chip pads and second load current chip pads. An interconnect substrate includes a first metal layer, a second metal layer, and an insulating material disposed between the first metal layer and the second metal layer. The first metal layer includes a pattern of holes, the second metal layer includes a pattern of protrusions, and the protrusions pass through the holes. The semiconductor transistor chip is mounted on the interconnect substrate with the first side facing the interconnect substrate. The first metal layer is connected to a plurality of the first load current chip pads and the second metal layer is connected via the pattern of protrusions to a plurality of the second load current chip pads.

A logic die for performing a through silicon via (TSV) repair operation and a semiconductor device including the logic die are provided. The semiconductor device includes the logic die including a memory controller and an interface circuit, a plurality of core dies stacked in a vertical direction on the logic die, each of the plurality of core dies including a memory cell array, and a plurality of through silicon vias (TSVs) configured to electrically connect the logic die to the plurality of core dies, the plurality of TSVs including a plurality of operation TSVs and at least one redundancy TSV. The interface circuit includes a plurality of TSV circuit blocks electrically connected to the plurality of TSVs, respectively, and a TSV repair logic configured to perform a repair operation on a first TSV, in which a defect occurs and a first TSV circuit block, electrically connected to the first TSV.

A semiconductor device, including: a substrate having a mounting surface; a semiconductor element mounted on the mounting surface of the substrate; and a positive electrode terminal and a negative electrode terminal disposed on the substrate. Each of the positive electrode terminal and the negative electrode terminal has at least one rising portion, to thereby have a total of at least three rising portions, each extending in a plane that intersects the mounting surface of the semiconductor element. Each of the rising portion of the positive electrode terminal faces one of the rising portions of the negative electrode terminal in a first direction.