A semiconductor device includes a semiconductor substrate, a temperature sensing diode provided on the semiconductor substrate, and a protective diode provided on the semiconductor substrate and connected in inverse parallel to the temperature sensing diode, wherein the temperature sensing diode includes a first anode layer that is a p-type semiconductor layer, and a first cathode layer that is adjacent to the first anode layer in plan view and is an n-type semiconductor layer, the protective diode includes a second anode layer that is a p-type semiconductor layer, and a second cathode layer that is adjacent to the second anode layer in plan view and is an n-type semiconductor layer, and a pn junction area of the second anode layer and the second cathode layer in the protective diode is larger than a pn junction area of the first anode layer and the first cathode layer in the temperature sensing diode.

In an electronic module, electrode pads of a first circuit component and electrode pads of a second circuit component are arranged such that conductive bonding members disposed between the electrode pads of the first circuit component and the electrode pads of the second circuit component form bonding member groups, each of which includes two or more conductive bonding members arranged along one direction in a plane direction of the first circuit component, with the one direction being defined as an extension direction of each of the bonding member groups. Each of reinforcing members is disposed apart from an adjacent bonding member group among the bonding member groups, and each of the reinforcing members has a first portion that extends along a direction intersecting with the extension direction of the adjacent bonding member group, and a second portion that extends along the extension direction of the adjacent bonding member group.

According to an embodiment, a semiconductor device includes a semiconductor chip having a first surface on which a source electrode and a gate electrode are provided and a second surface that is opposed to the first sur face and on which a drain electrode is provided, a source terminal having a fourth surface exposed from a third surface of a package and a fifth surface coupled to the source electrode and having a shape different from a sha pe of the fourth surface, a gate terminal having a sixth surface exposed from the third surface of the package and a seventh surface coupled to the gate electrode and having a shape different from a shape of the sixth surface, and a drain terminal coupled to the drain electrode and having an eighth surface exposed from the third surface of the package.

A semiconductor device includes a semiconductor element, a sealing body, and a plurality of terminals. The sealing body seals the semiconductor element therein. The terminals are electrically connected to the semiconductor element inside of the sealing body, and project from the sealing body. Each of the terminals has a rough surface area having a larger surface roughness than a peripheral area in a section in a longitudinal direction of the terminal.

A semiconductor device includes a semiconductor element, a sealing body, and a plurality of terminals. The sealing body seals the semiconductor element therein. The terminals are electrically connected to the semiconductor element inside of the sealing body, and project from the sealing body. Each of the terminals has a rough surface area having a larger surface roughness than a peripheral area in a section in a longitudinal direction of the terminal.

A semiconductor device includes: a conductive layer including a mounting surface; a first semiconductor element bonded to the mounting surface; a first terminal electrically connected to the first semiconductor element; and a first bonding layer electrically bonding the conductive layer and the first terminal. The conductive layer includes a first end surface, and a first peripheral surface located inward of the conductive layer from the first end surface as viewed in a first direction. The conductive layer includes a first engagement portion defined by the first peripheral surface. The first terminal includes a first bonding portion electrically bonded to the first engagement portion via the first bonding layer. As viewed in the first direction, the first bonding portion overlaps with the first engagement portion.

A first terminal is provided on a first surface of the first semiconductor package and electrically connected to a first pole side of the first semiconductor chip. A first output terminal is provided on a second surface of the first semiconductor package and electrically connected to a second pole side of the first semiconductor chip. A second output terminal is provided on a third surface of the second semiconductor package and electrically connected to the first pole side of the second semiconductor chip. A second terminal is provided on the third surface of the second semiconductor package and electrically connected to the second pole side of the second semiconductor chip. The first output terminal is connected to the second output terminal. A bus bar is connected to the second terminal and extends from the second terminal in a direction of the first surface on which the first terminal is provided.

A first terminal is provided on a first surface of the first semiconductor package and electrically connected to a first pole side of the first semiconductor chip. A first output terminal is provided on a second surface of the first semiconductor package and electrically connected to a second pole side of the first semiconductor chip. A second output terminal is provided on a third surface of the second semiconductor package and electrically connected to the first pole side of the second semiconductor chip. A second terminal is provided on the third surface of the second semiconductor package and electrically connected to the second pole side of the second semiconductor chip. The first output terminal is connected to the second output terminal. A bus bar is connected to the second terminal and extends from the second terminal in a direction of the first surface on which the first terminal is provided.

A hybrid power phase leg includes a phase node, a heatsink, a first semiconductor switch, and a second semiconductor switch. The first semiconductor switch includes a first cooling side, a first power node that neighbors the first cooling side, and a first switching node. The first cooling side is thermally connected to the heatsink and the first switching node is electrically connected to the phase node. The first switching node pulls the phase node toward a positive voltage rail while in a conductive state. The second semiconductor switch includes a second cooling side, a second power node that neighbors the second cooling side, and a second switching node. The second cooling side is thermally connected to the heatsink and the second switching node is electrically connected to the phase node. The second switching node pulls the phase node toward a negative voltage rail while in the conductive state.

Provided is a semiconductor device that can suppress deterioration of assemblability and can achieve downsizing. The semiconductor device includes a base member, a first semiconductor element, and a second semiconductor element. The second semiconductor element has a planar size smaller than that of the first semiconductor element. The first semiconductor element and the second semiconductor element are arranged in a first direction. In the base member, a first groove is formed to surround the first semiconductor element, a second groove is formed to surround the second semiconductor element. The first groove and the second groove overlap each other in a region between the first semiconductor element and the second semiconductor element. In a second direction, a distance between portions of the second groove disposed to sandwich the second semiconductor element is smaller than a distance between portions of the first groove disposed to sandwich the first semiconductor element.