Disclosed in the present invention is a method for predicting a delay at multiple corners for a digital integrated circuit, which is applicable to the problem of timing signoff at multiple corners. In the aspect of feature engineering, a path delay relationship at adjacent corners is extracted by using a dilated convolutional neural network (Dilated CNN), and learning is performed by using a bi-directional long short-term memory model (Bi-directional Long Short-Term Memory, BLSTM) to obtain topology information of a path. Finally, prediction results of a path delay at a plurality of corners are obtained by using an output of a multi-gate mixture-of-experts network model (Multi-gate Mixture-of-Experts, MMoE). Compared with a conventional machine learning method, the present invention can achieve prediction with higher precision through more effective feature engineering processing in a case of low simulation overheads, and is of great significance for timing signoff at multiple corners of a digital integrated circuit.

Example embodiments relate to a method for modeling power consumption of an integrated circuit, the method may comprise, determining, by the processor, a hierarchy structure regarding a gating level according to a clock flow of a plurality of clock gating cells included in the integrated circuit, determining, by the processor, a first clock gating domain corresponding to a first clock gating cell and a second clock gating domain corresponding to a second clock gating cell located in a lower level of the hierarchy of the first clock gating cell based on the hierarchy structure, calculating, by the processor, power consumption of the second clock gating domain based on a first logic level of a first clock gating enable signal applied to the first clock gating cell, and modeling, by the processor, power consumption of the integrated circuit based on the power consumption of the second clock gating domain.

IR drop predictions are obtained using a maximum convolutional neural network. A circuit structure is partitioned into a grid. For cells of the circuit structure in sub-intervals of a clock period, power consumption of the cell is amortized into a set of grid tiles that include portions of the cell, thus forming a set of power maps. The power maps are applied to a neural network to generate IR drop predictions for the circuit structure.

Systems and methods for context aware circuit design are described herein. A method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.

A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

Provided are a device and method for updating a register transfer level (RTL) power model for power consumption analysis of a semiconductor circuit by at least one processor. The method includes receiving a test scenario including a plurality of time slots, inputting the test scenario to an initial power model and identifying a first set of time slots related to a power state which is not defined by the initial power model among the plurality of time slots, determining a power value for a specific power state related to a second set of time slots which is a subset of the first set of time slots, and updating the initial power model on the basis of the specific power state and the determined power value. Each of the plurality of time slots is related to one power state.

A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.

A computer-readable storage medium that stores computer program code which, when executed by one or more processors, causes the one or more processors to execute tools for designing an integrated circuit (IC). The tools include a placing and routing tool that generates layout data and wire data corresponding to a net included in the IC by placing and routing standard cells defining the IC, the wire data including physical information of a wire implementing the net, and a timing analysis tool that calculates a wire delay with respect to the wire corresponding to the net, based on the physical information, updates the wire delay based on process variation of the wire, and calculates a timing slack by using the updated wire delay.

A method and a system of predicting an electric system load based on wavelet noise reduction and empirical mode decomposition-autoregressive integrated moving average (EMD-ARIMA) are provided. The method and the system belong to a field of electric system load prediction. The method includes the following steps. Raw load data of an electric system is obtained first. Next, noise reduction processing is performed on the load data through wavelet analysis. The noise-reduced load data is further processed through an EMD method to obtain different load components. Finally, ARIMA models corresponding to the different load components are built. Further, the ARIMA models are optimized through an Akaike information criterion (AIC) and a Bayesian information criterion (BIC). The load components obtained through predicting the different ARIMA models are reconstructed to obtain a final prediction result, and accuracy of load prediction is therefore effectively improved.

Systems and methods for demonstrating power control system (PCS) operating sequences provide a model builder and a sequence builder. The PCS model builder allows a user to build a graphical model of a PCS using drag-and-drop objects representing PCS components, such as generators, circuit breakers, transfer switches, and the like. The PCS sequence builder allows the user to enter plain language commands that represent operations performed by the model objects. The model builder then graphically animates the model according to the plain language commands. Animation may include changing an image color, shape, configuration, position, orientation, or size for the model objects. This allows any user to graphically demonstrate how a PCS would work before resources are invested toward developing the PCS.