An integrated circuit with mixed poly pitch cells with a plurality of different pitch sizes is disclosed. The integrated circuit includes: at least a minimum unit each with at least a first number of first poly pitch cells with a first pitch size, and a second number of second poly pitch cells with a second pitch size, the first pitch size PP is different from the second pitch size PP1, the greatest common divisor of the first pitch size PP and the second pitch size PP1 is GCD, wherein GCD is an integer greater than 1; a gate length of the first pitch size is Lg; a gate length of the second pitch size is Lg1; Lg and Lg1 are capable of being extended to achieve G-bias for power and speed optimization of the minimum unit and the integrated circuit.

A method includes: generating first specification data of a semiconductor device; performing, to the first specification data, a first evaluation operation corresponding to a first physical feature to the first specification data, to generate first parameters; performing, to the first specification data, a second evaluation operation corresponding to a second physical feature different from the first physical feature, to generate second parameters; comparing the first parameters and the second parameters with preset parameters; and when the first parameters and the second parameters meet the preset parameters, manufacturing the semiconductor device according to the first specification data.

A semiconductor device includes: active regions extending in a first direction; in a first metal layer on a first side of the active regions, first segments including as follows, first and second rails extending in the first direction, and first fingers between the first and second rails, each of the first fingers extending in a second direction substantially perpendicular to the first direction, and the first fingers extending across one or more of the active regions; and the first and second rails and the first fingers representing a ladder arrangement in which the first fingers representing rungs of the ladder arrangement and the first and second rails representing siderails of the ladder arrangement.

A semiconductor device includes a first circuit element, a layer of dielectric material, a first wire and a second wire in the layer of dielectric material, and an array of wires in the layer of dielectric material, wherein a first wire at a first track in the array of wires is electrically connected to the first circuit element, the first wire having a first width, a second wire at a second track in the array of wires has a second width different from the first width, and a third track in the array of wires between the first track and the second track is an empty track, and wherein the first wire is asymmetric with respect to the first track in the array of wires.

A computer system may receive a layout of a data center, the layout of the data center identifying physical locations of a plurality of server racks, electrical distribution feeds, and uninterruptible power supplies. The computer system may receive a fault domain configuration for the datacenter, the fault domain configuration identifying virtual locations of a plurality of logical fault domains for distributing one or more instances so that the instances are stored on independent physical hardware devices within a single availability fault domain. The computer system may determine the configuration for the data center by assigning the plurality of fault domains to a plurality of electrical zones, wherein each electrical zone provides a redundant electrical power supply across the plurality of logical fault domains in an event of a failure of one or more electrical distribution feeds. The computer system may display the configuration for the data center on a display.

An integrated circuit with mixed poly pitch cells with a plurality of different pitch sizes is disclosed. The integrated circuit includes: at least a minimum unit each with at least a first number of first poly pitch cells with a first pitch size, and a second number of second poly pitch cells with a second pitch size, the first pitch size PP is different from the second pitch size PP1, the greatest common divisor of the first pitch size PP and the second pitch size PP1 is GCD, wherein GCD is an integer greater than 1; a gate length of the first pitch size is Lg; a gate length of the second pitch size is Lg1; Lg and Lg1 are capable of being extended to achieve G-bias for power and speed optimization of the minimum unit and the integrated circuit.

Disclosed are a chip power consumption analyzer and an analyzation method thereof. The analyzation method includes the following. Design information of a circuit is received. A plurality of clock arriving times of a plurality of circuit cells in the circuit are calculated based on the design information, and a base cell type is set among a plurality of cell types according to the clock arriving times. Base demand current information of the base cell type is established, and a plurality of demand current information of the circuit cells is obtained. A plurality of demand peak currents of a plurality of bump current sources are predicted according to the demand current information and a plurality of position information of the circuit cells.

An integrated circuit (IC) device includes a plurality of first doped regions of a first semiconductor type over at least one first well region of the first semiconductor type, and a second doped region of a second semiconductor type over a second well region of the second semiconductor type. The second semiconductor type is different from the first semiconductor type. The plurality of first doped regions is arranged along a first direction. Each of the plurality of first doped regions has a first length in the first direction. The second doped region extends in the first direction between at least two first doped regions among the plurality of first doped regions over a second length greater than the first length.

An object of the present disclosure is to accurately simulate the operation of a CSTBT. The simulation model of a CSTBT includes a MOSFET, a diode whose cathode is connected to the drain of the MOSFET, capacitance C.sub.GE connected between a source and a gate of the MOSFET, capacitance C.sub.CG connected between a gate of the MOSFET and an anode of the diode, capacitance C.sub.CE connected between a source of the MOSFET and the anode of the diode, capacitance C.sub.DG connected between the drain and the gate of the MOSFET, and a behavioral power source V.sub.DG connected in series to the capacitance C.sub.DG between the drain and the gate of the MOSFET. The behavioral power source V.sub.DG performs a switching operation when gate-emitter voltage V.sub.GE of the CSTBT reaches a predetermined threshold value.

A method and an apparatus of designing an integrated circuit are provided. The method includes: S1, loading a power fill to a circuit layout with original metal lines; S2, checking whether a current layout includes a region with a spacing error; if yes, performing S3; otherwise, outputting the current layout; and S3, pruning a power fill shape corresponding to the region with a spacing error by a predetermined spacing width delta, and returning to the S2.