A display apparatus includes a circuit board including a driving circuit, a pixel array on the circuit board and including unit pixels, each of the unit pixels including a plurality of subpixels, and a plurality of microlenses respectively on the plurality of subpixels, where the pixel array further includes a plurality of light-emitting diode (LED) cells each respectively including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer that are sequentially stacked, a passivation layer on side surfaces and lower surfaces of the plurality of LED cells, a reflective layer on the passivation layer, the reflective layer configured to emit light toward upper surfaces of the plurality of LED cells, a gap-fill insulating layer on the side surfaces and lower surfaces of the plurality of LED cells, and a first connection electrode on the gap-fill insulating layer, and connected to the first conductivity-type semiconductor layers.

A stacked chip assembly for a display system may include a front plane die and one or more backplane dies, such as a first backplane die and a second backplane die. The front plane die may include a plurality of light emitting diodes (LEDs). The one or more backplane dies may be stacked vertically relative to the front plane die. In some implementations, the first backplane die may include a first portion of metal oxide semiconductor field effect transistor (MOSFET) display circuitry coupled with the plurality of LEDs, and the second backplane die may include a second portion of MOSFET display circuitry coupled with the first portion of MOSFET display circuitry. In some implementations, the backplane die may include display circuitry that is partitioned between analog circuitry in a first layer and digital circuitry in a second layer. Other aspects are also described and claimed.

A stacked chip assembly for a display system may include a front plane die and one or more backplane dies, such as a first backplane die and a second backplane die. The front plane die may include a plurality of light emitting diodes (LEDs). The one or more backplane dies may be stacked vertically relative to the front plane die. In some implementations, the first backplane die may include a first portion of metal oxide semiconductor field effect transistor (MOSFET) display circuitry coupled with the plurality of LEDs, and the second backplane die may include a second portion of MOSFET display circuitry coupled with the first portion of MOSFET display circuitry. In some implementations, the backplane die may include display circuitry that is partitioned between analog circuitry in a first layer and digital circuitry in a second layer. Other aspects are also described and claimed.

A wafer includes: a substrate; a plurality of light emitting elements on the substrate, each of the plurality of light emitting elements includes a semiconductor stack, a first contact electrode, and a second contact electrode; a plurality of pin pads on the substrate and including a semiconductor stack; and a plurality of connectors connecting different pin pads to each of the first contact electrode and the second contact electrode of a light emitting element from among the plurality of light emitting elements.

A wafer includes: a substrate; a plurality of light emitting elements on the substrate, each of the plurality of light emitting elements includes a semiconductor stack, a first contact electrode, and a second contact electrode; a plurality of pin pads on the substrate and including a semiconductor stack; and a plurality of connectors connecting different pin pads to each of the first contact electrode and the second contact electrode of a light emitting element from among the plurality of light emitting elements.

A display device includes a pixel electrode and a common electrode disposed on a substrate. An organic layer is disposed on the pixel electrode and the common electrode. A light emitting element is disposed on the organic layer and includes a semiconductor stack and a first and second contact electrode. A first connection electrode connects the first contact electrode and the pixel electrode. A second connection electrode connects the second contact electrode and the common electrode. First and second side electrodes are disposed on a side of the light emitting element and a top surface of the connection electrodes. First and second slope inclined layers are disposed on a side surface of the side electrodes and a second slope inclined layer. The side electrodes have downwardly concave structures between the side surface of the light emitting element and the slope inclined layer.

A display device includes a pixel electrode and a common electrode disposed on a substrate. An organic layer is disposed on the pixel electrode and the common electrode. A light emitting element is disposed on the organic layer and includes a semiconductor stack and a first and second contact electrode. A first connection electrode connects the first contact electrode and the pixel electrode. A second connection electrode connects the second contact electrode and the common electrode. First and second side electrodes are disposed on a side of the light emitting element and a top surface of the connection electrodes. First and second slope inclined layers are disposed on a side surface of the side electrodes and a second slope inclined layer. The side electrodes have downwardly concave structures between the side surface of the light emitting element and the slope inclined layer.

A display device includes a first alignment electrode and a second alignment electrode spaced apart from each other and disposed on a substrate, light emitting elements disposed between the first alignment electrode and the second alignment electrode, and an amorphous silicon layer disposed on the light emitting elements. The amorphous silicon layer includes an electrode portion disposed on a first end portion and a second end portion of each of the light emitting elements, and an insulating portion.

A display device includes a first alignment electrode and a second alignment electrode spaced apart from each other and disposed on a substrate, light emitting elements disposed between the first alignment electrode and the second alignment electrode, and an amorphous silicon layer disposed on the light emitting elements. The amorphous silicon layer includes an electrode portion disposed on a first end portion and a second end portion of each of the light emitting elements, and an insulating portion.

A pixel includes a light-emitting diode, a first transistor connected between a first voltage line and the light-emitting diode, and configured to control a current supplied to the light-emitting diode, a second transistor connected between a data line and a first node connected to a first terminal of the first transistor, and including a 2-1 transistor connected between the data line and a fourth node, and a 2-2 transistor in series with the 2-1 transistor and connected between the fourth node and the first node, a third transistor connected between a second node connected to a gate of the first transistor and a third node connected to a second terminal of the first transistor, a fifth transistor connected between the first voltage line and the first node, and a sixth transistor connected between the third node and the light-emitting diode.