An IC structure includes a first fin structure, a first epitaxial structure, first sidewall spacers, a second fin structure, a second epitaxial structure, and second sidewall spacers. The first epitaxial structure is on the first structure. The first sidewall spacers are respectively on opposite sidewalls of the first epitaxial structure. The second epitaxial structure is on the second fin structure. The second sidewall spacers are respectively on opposite sidewalls of the second epitaxial structure. A height difference between the second sidewall spacers is greater than a height difference between the first sidewall spacers.

A semiconductor device includes a substrate having a first region and a second region, a first transistor in the first region, and a second transistor in the second region. The first transistor includes a first gate structure having an interfacial layer, a first high-k region over the interfacial layer, and a conductive layer over the first high-k region. The second transistor includes a second gate structure having the interfacial layer, a second high-k region over the interfacial layer, and the conductive layer over the second high-k region. The first high-k region is thicker than the second high-k region. The first transistor includes a first channel under the first gate structure. The first channel has first and second semiconductor materials alternately stacked. The first transistor includes a first source/drain (S/D) feature interfacing with both the first and second semiconductor materials in the first channel of the first transistor.

A semiconductor device includes a semiconductor substrate, a first semiconductor stack, a second semiconductor stack, a first gate structure, and a second gate structure. The semiconductor substrate comprising a first device region and a second device region. The first semiconductor stack is located on the semiconductor substrate over the first device region, and has first channels. The second semiconductor stack is located on the semiconductor substrate over the second device region, and has second channels. A total number of the first channels is greater than a total number of the second channels. The first gate structure encloses the first semiconductor stack. The second gate structure encloses the second semiconductor stack.

A method includes providing a substrate having an epitaxial stack of layers including a plurality of semiconductor channel layers interposed by a plurality of dummy layers. The substrate includes a first device region and a second device region. An etch process is performed to remove a first portion of the epitaxial stack of layers from the second device region to form a trench in the second device region. The removed first portion of the epitaxial stack of layers includes at least one semiconductor channel layer of the plurality of semiconductor channel layers. An epitaxial layer is formed within the trench in the second device region and over the second portion of the epitaxial stack of layers. A top surface of the epitaxial layer in the second device region is substantially level with a top surface of the epitaxial stack of layers in the first device region.

Disclosed is a semiconductor device comprising a first channel region, a first dielectric structure on the first channel region, a first metal pattern spaced apart from the first dielectric structure, and a first dipole structure between the first metal pattern and the first dielectric structure. The first dipole structure includes a first dipole layer and a second dipole layer. The first dipole layer includes a first dipole element. The second dipole layer includes a second dipole element different from the first dipole element. A maximum oxidation number of the first dipole element is different from a maximum oxidation number of the second dipole element.

A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first channel structure positioned over a substrate, first source/drain (S/D) regions positioned on ends of the first channel structure, and a first gate structure disposed all around the first channel structure. The second transistor includes a second channel structure positioned over the first channel structure, second S/D regions positioned on ends of the second channel structure, and a second gate structure disposed all around the second channel structure. The second channel structure has a smaller dimension than the first channel structure in a horizontal direction substantially parallel to a working surface of the substrate.

This disclosure provides semiconductor device including a first transistor with a first gate terminal, a first source terminal, and the first drain terminal, the first transistor being a depletion mode transistor and including a plurality of two-dimensional carrier channels of a conductivity type being one of a n-type or a p-type conductivity. The semiconductor device also includes a second transistor with a second gate terminal, a second source terminal, and a second drain terminal, the second transistor being an enhancement mode transistor, a gate-source interconnect forming an electrical connection between the first gate terminal and the second source terminal, and a drain-source interconnect forming an electrical connection between the first source terminal and the second drain terminal. The first transistor and the second transistor are fabricated on the same wafer or substrate.

Semiconductor structures and methods of fabrication are provided. A method according to the present disclosure includes receiving a workpiece that includes an active region over a substrate and having first semiconductor layers interleaved by second semiconductor layers, and a dummy gate stack over a channel region of the active region, etching source/drain regions of the active region to form source/drain trenches that expose sidewalls of the active region, selectively and partially etching second semiconductor layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, forming channel extension features on exposed sidewalls of the first semiconductor layers, forming source/drain features over the source/drain trenches, removing the dummy gate stack, selectively removing the second semiconductor layers to form nanostructures in the channel region, forming a gate structure to wrap around each of the nanostructures. The channel extension features include undoped silicon.

An IC structure includes a first well region of a first conductivity type formed in a substrate, a second well region of a second conductivity type formed in the substrate, a first source/drain feature over the first well region, a second source/drain feature over the second well region. The second conductivity type is different than the first conductivity type. The IC structure further includes first sidewall spacers respectively on opposite sidewalls of the first source/drain feature, and second sidewall spacers respectively on opposite sidewalls of the second source/drain feature. A height difference between the second sidewall spacers is greater than a height difference between the first sidewall spacers.

A layout structure of a standard cell lying astride standard cell rows different in height is provided. A double-height cell is formed astride first and second cell rows. The height of the second cell is greater than the height of the first cell. The double-height cell includes a first logic circuit that receives an input signal and outputs a signal to an internal node and a second logic circuit that receives the signal from the internal node and outputs an output signal. Transistors constituting the first logic circuit are formed in a region of the first cell row, and transistors constituting the second logic circuit are formed in a region of the second cell row.