A method of manufacturing a semiconductor device includes forming a semiconductor device structure including a gate structure and source/drain regions disposed over a substrate, wherein the source/drain regions are embedded in the semiconductor device structure. An opening is formed in the semiconductor device structure over the source/drain region. A dopant is implanted into sidewalls of the opening. The opening is enlarged over the source/drain region. The source/drain region is exposed. A silicide layer is formed over the exposed source/drain region, and a conductive contact is formed in the opening.

A semiconductor device may include a first fin pattern, a first source/drain pattern on the first fin pattern, a second fin pattern spaced apart in a first direction from the first fin pattern, a second source/drain pattern on the second fin pattern, a first gate electrode overlapping the first fin pattern and extending in a second direction crossing the first direction, a second gate electrode overlapping the second fin pattern and extending in the second direction, and a first dummy structure between the first fin pattern and the second fin pattern and between the first gate electrode and the second gate electrode. The first dummy structure may include first to third line parts extending in the second direction, first and second connection parts connecting the first and second line parts to each other, and a third connection part connecting the second and third line parts to each other.

Provided is a semiconductor device which includes: an isolation structure; a 1.sup.st contact structure in the isolation structure; and a 2.sup.nd contact structure adjacent to and at a lateral side of the 1.sup.st contact structure, in the isolation structure, wherein at least one of the 1.sup.st contact structure and the 2.sup.nd contact structure has an extra isolation layer on a side surface thereof facing the other of the 1.sup.st contact structure and the 2.sup.nd contact structure.

A semiconductor device includes a substrate, a lower channel stack on the substrate, an upper channel stack on the lower channel stack, a gate electrode extending around the lower channel stack and the upper channel stack, a gate cut region that is on the substrate and includes an insulating material, a semiconductor material layer between the upper channel stack and the gate cut region, and an insulating layer that is between the semiconductor material layer and the upper channel stack.

Embodiments of the invention include a single stack dual channel gate-all-around nanosheet with strained PFET and bottom dielectric isolation NFET. A PFET comprising at least one silicon germanium channel is formed. An NFET comprising at least one silicon channel is formed, the PFET being positioned laterally to the NFET, the at least one silicon channel and the at least one silicon germanium channel being staggered in a vertical direction.

Semiconductor devices according to some example embodiments include: a substrate; first channel patterns and second channel patterns that are spaced apart from each other on the substrate; an insulation structure between the first channel patterns and the second channel patterns; a gate structure that surrounds the first channel patterns, the second channel patterns, and at least a part of the insulation structure; and a source/drain pattern that is at both sides of each of the first channel patterns and the second channel patterns, wherein the insulation structure includes a first embedded insulation layer that is between the first channel patterns and the second channel patterns and extend in a first direction and a second embedded insulation layer between the first embedded insulation layer and the first channel patterns, and portions of the second embedded insulation layer are spaced apart from each other in the first direction.

Semiconductor devices and manufacture methods thereof are provided. In one aspect, a semiconductor device includes a first transistor, where the first transistor includes first channel patterns stacked on a first active pattern with a first channel length and first source and drain patterns; and a second transistor, where the second transistor includes second channel patterns stacked on a second active pattern with a second channel length greater than the first channel length and second source and drain patterns. Each of the first source and drain patterns include a first high-resistivity bottom epitaxial layer, a first epitaxial layer, and a second epitaxial layer. Each of the second source and drain patterns includes a third epitaxial layer on the second active pattern and a fourth epitaxial layer. A bottom level of the first source and drain patterns is lower than a bottom level of the second source and drain patterns.

There is provided a semiconductor device with improved yield and performance. The semiconductor device includes a substrate including a first region and a second region and having a first conductivity type, first and second active patterns spaced apart by a first pitch, on the first region, a first gate structure intersecting the first and second active patterns, first epitaxial patterns each having a second conductivity type, different from the first conductivity type, and receiving the same voltage level, on both sides of the first gate structure on each of the first and second active patterns, third and fourth active patterns spaced apart by a second pitch, on the second region, a second gate structure intersecting the third and fourth active patterns, and second epitaxial patterns each having the second conductivity type, on the sides of the second gate structure on each of the third and fourth active patterns, wherein the first pitch is n times the second pitch (where n is a natural number of 2 or greater), and no epitaxial pattern having the second conductivity type is disposed between the first and second active patterns

A semiconductor device includes a first region in which a passive element is provided, a second region adjacent to the first region and in which an active element is provided, a lower interlayer insulating layer in the first region and the second region, an insulating pattern in the second region and on an upper surface of the lower interlayer insulating layer, the insulating pattern extending in a first direction, a substrate in the first region, on the upper surface of the lower interlayer insulating layer, and spaced apart from the insulating pattern in the first direction, the substrate including silicon, and a field insulating layer in the second region and on the upper surface of the lower interlayer insulating layer, the field insulating layer at least partially surrounding a sidewall of the insulating pattern.

A semiconductor device comprises a plurality of channel layers in a stacked configuration, and a gate structure disposed through respective ones of the plurality of channel layers. The gate structure is surrounded on at least three sides by portions of the respective ones of the plurality of channel layers. The gate structure is disposed from an uppermost channel layer of the plurality of channel layers to a lowermost channel layer of the plurality of channel layers.