A semiconductor device includes: a first substrate; a first fin protruding above the first substrate; first nanostructures over the first fin; a first gate structure around the first nanostructures; a first source/drain region adjacent to the first gate structure and contacting a first subset of the first nanostructures; a first dielectric structure between the first source/drain region and the first fin, where the first dielectric structure contacts a second subset of the first nanostructures; second nanostructures over the first fin and laterally spaced apart from the first nanostructures; a second gate structure around the second nanostructures; and a second source/drain region adjacent to the second gate structure and contacting the second nanostructures.

A source/drain region is formed for a nanostructure transistor of a semiconductor device such that the source/drain region includes a metal core. The metal core provides a greater amount of surface area for a front side source/drain contact and a back side source/drain contact to be coupled to the source/drain region than if the source/drain region were fully filled in with epitaxially-grown semiconductor material. The increased contact surface area provides for reduced contact resistance between the source/drain region and the front side and back side source/drain contacts because of the less-restricted current flow path between the source/drain region and the front side and back side source/drain contacts. The reduced contact resistance between the source/drain region and the front side and back side source/drain contacts enables a greater power efficiency to be achieved for the nanostructure transistor and/or enables increased switching speeds to be achieved for the nanostructure transistor.

Nanoribbon-based devices with separate gate, source, and/or drain contacts can enable forming multiple devices having one or more independent contacts from different nanoribbons in a stack. In one example, an integrated circuity structure includes a stack of two or more nanoribbons, a gate electrode material at least partially around portions of the two or more nanoribbons, and source or drain regions, where discontinuities (e.g., including an insulator material) may be present between portions of the gate electrode material and/or between portions of the source or drain regions. Independent contact structures may be coupled with the separate portions of the gate electrode material and/or with the separate portions of the source or drain regions.

A method includes forming a first multilayer stack in a first device region, forming a first gate stack over the first multilayer stack, forming a second multilayer stack in a second device region, forming a second gate stack over the second multilayer stack, etching the first multilayer stack to form a first source/drain recess, and etching the second multilayer stack to form a second source/drain recess. The method further includes forming a hard mask in the second source/drain recess, and forming a lower source/drain region in the first source/drain recess. After the lower source/drain region is formed, the hard mask is removed from the second source/drain recess. A first upper source/drain region and a second upper source/drain region are formed in the first source/drain recess and the second source/drain recess, respectively.

A plurality of SRAM cells include: a first SRAM cell; and a second SRAM cell aligned with the first SRAM cell in a first direction. In the first SRAM cell, lines corresponding to bit lines BLB and BL, respectively, are formed in an M1 interconnect layer that is a metal interconnect layer. In the second SRAM cell, lines corresponding to bit lines BLB and BL, respectively, are formed in a BM0 interconnect layer which is an interconnect layer on the back of a transistor.

A semiconductor device includes an active gate structure disposed over a substrate; first source/drain features disposed at two opposite sides of the active gate structure; a dielectric gate structure disposed over the substrate, the dielectric gate structure and the active gate structure stacked one over another along a vertical direction perpendicular to the substrate; and second source/drain features disposed at two opposite sides of the dielectric gate structure, where the first source/drain features and the second source/drain features are of different conductivity types.

A semiconductor device structure includes a plurality of transistors. Each of the plurality of transistors includes a nanostructure having a first dopant type, wherein the nanostructure extends in a first direction; a gate structure; a first source/drain (S/D) region; and a second S/D region. The semiconductor device structure further includes a second nanostructure offset from the plurality of transistors in a second direction, wherein the second nanostructure has a second dopant type opposite the first dopant type. The semiconductor device structure further includes a dielectric material in direct contact with the second nanostructure. The dielectric material is (1) aligned with at least one of the gate structure or the first S/D region in the second direction; or (2) extends in the first direction for a distance equal to or greater than a combined width of the gate structure, the first S/D region and the second S/D region.

Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a substrate; an insulator on an upper surface of the substrate; a transistor between the substrate and the insulator, the transistor comprising: channel layers that are spaced apart from each other in a first direction that is perpendicular to the upper surface of the substrate; and a gate structure on the channel layers and the insulator, wherein a width of the insulator in a second direction that is parallel with the upper surface of the substrate is equal or substantially equal to a width of an uppermost one of the channel layers in the second direction.

A semiconductor device includes a substrate, a first channel pattern on the substrate, the first channel pattern having a first width, a first gate electrode extending in a second direction, a first gate capping pattern on an upper surface of the first gate electrode, a second channel pattern spaced apart from the first channel pattern, the first channel pattern having a second width, a second gate electrode extending in the second direction on the second channel pattern, a second gate capping pattern on an upper surface of the second gate electrode, a source/drain pattern on at least one side of the second channel pattern, a first source/drain contact connected to the source/drain pattern, a second source/drain contact spaced apart from the first source/drain contact, and a contact isolation film between the first source/drain contact and the second source/drain contact. The second width is greater than the first width.

An integrated circuit device includes a gate line, a source/drain region adjacent to the gate line in a first direction, a backside via contact connected to the source/drain region, a backside power rail integrally connected to the backside via contact and spaced apart from the source/drain region in a second direction with the backside via contact therebetween, and a backside insulating pattern overlapping the gate line in the second direction and contacting a sidewall of the backside power rail in the first direction, wherein the backside insulating pattern includes a first backside insulating portion having a gradually increasing width in the first direction with an increasing distance from the gate line, and a second backside insulating portion integrally connected to the first backside insulating portion and having a gradually decreasing width in the first direction with an increasing distance from the gate line.