A method includes forming a source/drain region, forming a contact etch stop layer over the source/drain region, forming an inter-layer dielectric over the contact etch stop layer, forming a first contact plug in the inter-layer dielectric and the contact etch stop layer, and performing an etching process to form a trench in the inter-layer dielectric and the contact etch stop layer. The source/drain region and the first contact plug are exposed to the trench. The method further includes performing a silicide formation process to form a silicide region on a surface of the source/drain region, and etching a metal layer that is deposited on dielectric regions and in the trench. The dielectric regions are exposed at a time the silicide formation process is started. A second contact plug is formed in the trench.

A method of forming a semiconductor device includes: forming an electrically conductive feature over a substrate; forming a dielectric layer over the electrically conductive feature and the substrate; forming a layer of a polycrystalline material over the dielectric layer, where a first facet of the polycrystalline material and a second facet of the polycrystalline material have different lattice densities; selectively adsorbing molecules of a material on the first facet of the polycrystalline material; and after selectively adsorbing molecules of the material, performing a planarization process to the layer of the polycrystalline material, where the planarization process removes the polycrystalline material at a first removal rate at the first facet and removes the polycrystalline material at a second removal rate at the second facet, where the molecules of the material on the first facet cause a decrease in a difference between the first removal rate and the second removal rate.

A method includes forming a lower source/drain region and an upper source/drain region adjacent to a multi-layer stack, the multi-layer stack comprising dummy nanostructures that are alternatingly stacked with semiconductor nanostructures, the semiconductor nanostructures comprising lower semiconductor nanostructures and upper semiconductor nanostructures; removing the dummy nanostructures; forming first gate dielectrics around the lower semiconductor nanostructures and second gate dielectrics around the upper semiconductor nanostructures; forming a first work function metal layer over the first gate dielectrics and the second gate dielectrics; forming a first metal over the first work function metal layer; performing a first etch on the first metal to expose the first work function metal layer; performing a second etch on the first work function metal layer to expose the second gate dielectrics; forming a second work function metal layer over the second gate dielectrics; and forming a second metal over the second work function metal layer.

Gate stacks for stacked device structures, such as stacked transistors, and methods of fabrication thereof are disclosed. An exemplary method includes forming a semiconductor layer stack over a substrate. The semiconductor layer stack includes a first semiconductor layer disposed over a second semiconductor layer. The method further includes forming a first type metal gate layer around the second semiconductor layer. The method further includes, after forming an aluminum-containing isolation layer over the first type metal gate layer, forming a second type metal gate layer around the first semiconductor layer and over the aluminum-containing isolation layer. In some embodiments, the method further includes removing a native metal oxide layer from over the first type metal gate layer before forming the aluminum-containing isolation layer. In some embodiments, removing the native metal oxide layer from over the first type metal gate layer includes performing a chlorine-based gas treatment.

A vertically stacked semiconductor device and manufacturing method thereof. The method includes: sequentially providing a lower stack, an intermediate layer, and an upper stack on a substrate; patterning the lower stack, the intermediate layer, the upper stack and an upper portion of the substrate; forming a sacrificial gate on the substrate; forming a gate spacer on a sidewall of the sacrificial gate; patterning the lower stack, the intermediate layer, and the upper stack; selectively etching the sacrificial layer and the intermediate layer; filling a space released by selective etching the sacrificial layer and the intermediate layer with a dielectric material; forming a lower source/drain layer adjacent to an exposed side surface of the channel layer in the lower stack, forming an upper source/drain layer adjacent to an exposed side surface of the channel layer in the upper stack; replacing the sacrificial gate and the sacrificial layer with a gate stack.

A semiconductor device includes a substrate, first and second active patterns, first and second gate structures intersecting the first active pattern, third and fourth gate structures intersecting the second active pattern, first level wiring patterns disposed at a first level on the substrate and including first to fourth lower wiring patterns connected to the first to fourth gates, respectively, and a fifth lower wiring pattern, and second level wiring patterns disposed at a second level higher than the first level substrate and including a first upper wiring pattern and a second upper wiring pattern. The first upper wiring pattern connects the second lower wiring pattern to the third lower wiring pattern. A second upper wiring pattern connects the fourth lower wiring pattern to the fifth lower wiring pattern. The first lower wiring pattern is electrically connected to the fifth lower wiring pattern.

A method of forming a semiconductor device includes: forming a layer stack over a fin by successively forming a dielectric material, a sacrificial material, a first semiconductor material, and a second semiconductor material over the fin; forming a dummy gate structure over the layer stack; forming source/drain regions on opposing sides of the dummy gate structure; forming an inter-layer dielectric layer over the source/drain regions around the dummy gate structure; removing the dummy gate structure to expose a first portion of the layer stack; after removing the dummy gate structure, selectively removing the sacrificial material in the first portion of the layer stack, where after the selectively removing, the first semiconductor material and the second semiconductor material in the first portion of the layer stack form a first channel layer and a second channel layer, respectively; and forming a replacement gate structure around the first and the second channel layers.

A method includes providing a structure. The structure includes a stack of bottom channel layers, a stack of top channel layers disposed over the stack of bottom channel layers, an isolation feature sandwiched by the stack of bottom channel layers and the stack of bottom channel layers, and a first work function metal (WFM) layer wrapping around each of the bottom channel layers. The method further includes forming a second WFM layer wrapping around each of the top channel layers, forming a passivation layer on the second WFM layer by performing a gas treatment to the structure, and forming a metal fill layer over the passivation layer.

A semiconductor device includes a base structure extending in a first direction; gate electrodes disposed on the base structure, extending in a second direction, and spaced apart from each other in the first direction and the second direction; a plurality of channel layers disposed on the base structure, spaced apart from each other in a third direction, and surrounded by the gate electrodes; source/drain regions connected to the plurality of channel layers on opposite sides of the gate electrodes; an isolation structure separating the gate electrodes, the plurality of channel layers, and the source/drain regions in the second direction, and extending in the first direction; and a gate connection layer electrically connecting a first gate electrode and a second gate electrode spaced apart from each other in a fourth direction, the gate connection layer disposed on the isolation structure and contacting an upper surface thereof.

A semiconductor device includes an active region extending in a first direction; a gate structure on the active region and extending in a second direction intersecting the first direction; source/drain regions on side surfaces of the gate structure and on the active region; front side contacts on a first side of the source/drain regions; backside contacts at least partially penetrating the active region and on a second side of the source/drain regions opposite the first side; and an interlayer insulating layer on the gate structure, on the source/drain regions, and on the front side contacts. An entire upper surface of the gate structure that is opposite the active region in a third direction perpendicular to the first and second directions is in contact with the interlayer insulating layer.