Semiconductor device structures are provided. The semiconductor device structure includes a semiconductor substrate with an original semiconductor surface and an active region, a STI region surrounding the active region, a transistor formed based on the active region and including a gate structure, a first conductive region, a second conductive region and a channel region between the first and second conductive regions, an interconnection structure extending beyond the transistor, and a connecting plug electrically connecting the interconnection structure to the first conductive region of the transistor. The first conductive region includes an epitaxial semiconductor material. The interconnection structure is disposed under the original semiconductor surface and within the STI region.

Horizontal gate-all-around devices and methods of manufacturing are described. The hGAA devices include a fully-depleted silicon-on-insulator (FD-SOI) under the channel layers in the same footprint as the hGAA. The buried dielectric insulating layer of the FD-SOI includes one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high-k material, and the buried dielectric insulating layer has a thickness in a range of from 0 nm to 10 nm.

The disclosure relates to a complementary field effect transistor, CFET, structure. The CFET structure comprises: a first CFET element which is arranged in a first row of the CFET structure; and a second CFET element which is arranged in a second row of the CFET structure, wherein the second row is arranged laterally offset to the first row; wherein the first and the second CFET element each comprise: a first transistor structure, and a second transistor structure which is arranged above the first transistor structure. The CFET structure further comprises a shared signal routing structure which is arranged between the first and the second CFET element; wherein the shared signal routing structure is electrically connected to the first and/or the second transistor structure of the first and/or of the second CFET element, respectively.

A method for forming a 2D channel field-effect transistor device is provided. The method includes forming a device layer stack on a substrate. The device layer stack includes lower and upper sacrificial layers and a channel layer of a 2D material. The method further includes embedding the device layer stack in a dummy layer, forming a gate cavity in the dummy layer, and removing the sacrificial layers from the device layer stack by etching the sacrificial material from the gate cavity. After removing the sacrificial layers, the method includes forming an oxide liner along sidewalls of the gate cavity including an oxidation process to oxidize a thickness portion of the dummy layer, forming a gate stack in the gate cavity to surround the channel layer, forming source/drain contact cavities in the dummy layer, forming source/drain contacts in the source/drain contact cavities, and replacing the dummy layer with a dielectric layer.

A semiconductor structure includes a gate structure region; a source region and a drain region disposed on two sides of the gate structure respectively. The gate structure region includes a channel region and a gate region disposed from inside to outside. The channel region is surrounded inside an inner cavity of the gate region and attached to the source region, the drain region, and the gate region, and an ion doping type of the drain region, an ion doping type of the source region and an ion doping type of the channel region are same.

A semiconductor device, including: a lower interlayer insulating layer; an insulating pattern extending in a first horizontal direction on an upper surface of the lower interlayer insulating layer; a plurality of nanosheets on the insulating pattern and spaced apart in a vertical direction; an active cut including a first portion penetrating the lower interlayer insulating layer and the insulating pattern in the vertical direction, and a second portion separating the plurality of nanosheets in the first horizontal direction on an upper surface of the first portion, wherein a lower surface of the second portion is on an upper surface of the insulating pattern, and wherein the second portion is on inner sidewalls of the plurality of nanosheets in the first horizontal direction; a first source/drain region on a first side of the active cut on the insulating pattern, wherein the first source/drain region is on first outer sidewalls of the plurality of nanosheets; a second source/drain region on a second side of the active cut opposite to the first side of the active cut in the first horizontal direction on the insulating pattern, wherein the second source/drain region is on second outer sidewalls of the plurality of nanosheets; and a bottom source/drain contact penetrating the lower interlayer insulating layer and the insulating pattern in the vertical direction, wherein the bottom source/drain contact is electrically connected to the second source/drain region, and wherein the bottom source/drain contact overlaps the first portion of the active cut in the first horizontal direction, wherein a width of the upper surface of the first portion of the active cut in the first horizontal direction is smaller than a width of a lower surface of the first portion of the active cut in the first horizontal direction.

An integrated circuit device may include a nanosheet stack including a plurality of nanosheets, a gate line at least partially surrounding each of the plurality of nanosheets, the gate line including a main gate part and a sub-gate part, a source/drain region in contact with the plurality of nanosheets, and an inner insulating spacer between the sub-gate part and the source/drain region, wherein a first sidewall and a second sidewall each include a part recessed toward an inside of the inner insulating spacer, the first sidewall facing the source/drain and the second sidewall opposite to the first sidewall.

A semiconductor structure includes a substrate; a plurality of isolation stack layers located on the substrate, an isolation stack layer of the plurality of isolation stack layers including a plurality of isolation layers spaced apart in a vertical direction; and a plurality of channel layer structures each located on one isolation stack layer, a channel layer structure of the plurality of channel layer structures including a plurality of channel layers spaced apart in the vertical direction, sidewalls of adjacent channel layer structures forming a groove penetrating through the plurality of channel layer structures in the vertical direction, and the groove further extending into the plurality of isolation stack layers in the vertical direction.

A layout structure of a standard cell lying astride standard cell rows different in height is provided. A double-height cell is formed astride first and second cell rows. The height of the second cell is greater than the height of the first cell. The double-height cell includes a first logic circuit that receives an input signal and outputs a signal to an internal node and a second logic circuit that receives the signal from the internal node and outputs an output signal. Transistors constituting the first logic circuit are formed in a region of the first cell row, and transistors constituting the second logic circuit are formed in a region of the second cell row.

A semiconductor device structure and methods of forming the same are described. The structure includes a gate dielectric layer disposed over a substrate, a gate electrode layer disposed over the gate dielectric layer, and a first gate spacer disposed adjacent the gate dielectric layer. The first gate spacer includes an inner surface facing the gate dielectric layer and an outer surface opposite the inner surface, and the first gate spacer includes a fluorine concentration that decreases from the inner surface and the outer surface towards a center of the first gate spacer. The structure further includes a second gate spacer disposed on the outer surface of the first gate spacer, and the second gate spacer includes a fluorine concentration that decreases from an outer surface towards an inner surface.