A semiconductor device includes first source/drain patterns spaced apart in a first direction on a first region of a substrate, a first gate structure extending in a second direction intersecting the first direction, second source/drain patterns spaced apart in the first direction on a second region of the substrate, a second gate structure extending in the second direction, a first internal gate spacer between the first gate structure and one of the first source/drain patterns, and a second internal gate spacer between the second gate structure and one of the second source/drain patterns. The first and second internal gate spacers have first and second thicknesses, respectively, in the first direction. The first thickness of the first internal gate spacer at a center point thereof along the second direction is different from the second thickness of the second internal gate spacer at a center point thereof along the second direction.

A semiconductor device includes a substrate, a transistor stack on the substrate, a first source/drain structure on a first side of the transistor stack, and a second source/drain structure on a second side of the transistor stack, where the transistor stack includes a lower transistor on the substrate, the lower transistor including a lower channel layer and a lower gate structure surrounding the lower channel layer, an upper transistor on the lower transistor, the upper transistor including an upper channel layer and an upper gate structure surrounding the upper channel layer, and a first connecting layer between the lower gate structure and the upper gate structure, and the first source/drain structure and the second source/drain structure are connected via the first connecting layer.

A semiconductor device may include a substrate that comprises a first active pattern and a second active pattern that are spaced apart from each other; a first channel structure on the first active pattern; a first source/drain pattern on the first channel structure; a first pillar structure between the first active pattern and the second active pattern; and a second pillar structure on the first pillar structure, wherein the first pillar structure comprises a first upper surface that is in contact with the second pillar structure and a second upper surface that is higher than the first upper surface, wherein the first upper surface of the first pillar structure is lower than an uppermost surface of the first channel structure, wherein the second upper surface of the first pillar structure is lower than an upper surface of the second pillar structure.

A method of forming a portion of a gate-all-around field-effect transistor (GAA FET) includes performing an isotropic etch process to partially etch a substrate from source/drain (S/D) recesses extending into a front inter-layer dielectric (ILD) formed on the substrate, performing a substrate nitridation process to form nitride layers on inner surfaces of the S/D recesses, and performing a substrate removal process to selectively etch the substrate while protecting underlying extension regions within the S/D recesses by the nitride layers and form ILD recesses.

There is provided a semiconductor device with improved integration and performance. The semiconductor device includes a substrate, a first lower active pattern, a first upper active pattern on the first lower active pattern, a first gate structure on the first lower active pattern and the first upper active pattern, a second lower active pattern spaced apart from the first lower active pattern, a second upper active pattern on the second lower active pattern and spaced apart from the first upper active pattern, a second gate structure on the second lower active pattern and the second upper active pattern, a first source/drain contact electrically connected to a first lower source/drain region of the first lower active pattern and a first upper source/drain region of the first upper active pattern and a first back connecting wire and electrically connecting the first source/drain contact and the second gate structure.

A semiconductor device includes a substrate insulating layer, a gate structure extending in a first direction on the substrate insulating layer, a plurality of channel layers spaced apart from each other in a second direction, the second direction perpendicular to an upper surface of the substrate insulating layer, the plurality of channel layers on the substrate insulating layer and surrounded by the gate structure, a first source/drain region and a second source/drain region, on both sides of the gate structure and connecting to the plurality of channel layers, a first spacer layer below the first source/drain region, and a second spacer layer below the second source/drain region, and a backside contact plug partially recessing a lower surface of the first source/drain region through the substrate insulating layer and the first spacer layer.

A semiconductor device includes a substrate insulating layer including an insulating pattern, a first gate structure and a second gate structure overlapping the insulating pattern, first semiconductor patterns spaced apart from each other and second semiconductor patterns spaced apart from each other, first and second source/drain regions respectively connected to the first and second semiconductor patterns, a first separation pattern extending between the first and second gate structures, the first separation pattern insulating the first and second gate structures from each other, a second separation pattern extending into respective at least portions of ones of the first semiconductor patterns and ones of the second semiconductor patterns, and a backside contact plug extending into the substrate insulating layer and connected to at least some of the source/drain regions. At least one of the first and second separation patterns includes an air gap.

Embodiments of the present disclosure provide a GAA device fabricated from a substrate having a (551)<110> top surface. Selecting the (551)/<110> substrate enables channel height scaling with improved hole mobility and without sacrificing electron mobility.

A method of manufacturing a semiconductor device includes forming an interfacial layer over a channel region and forming a metal-containing layer over the interfacial layer. A metal silicate layer is formed over the channel region after forming the metal-containing layer. A portion of the metal silicate layer is removed. A gate dielectric layer is formed over the channel region after removing the portion of the metal silicate layer, and a gate electrode layer is formed over the gate dielectric layer.

An integrated circuit comprising: a plurality of devices arranged on a front side of a substrate; a first backside pattern and a second backside pattern, wherein the first backside pattern and the second backside pattern extend in a first direction along a first track in a first backside wiring layer, wherein the first backside wiring layer is on a back side of the substrate, and wherein the first backside pattern and the second backside pattern are configured to receive a first supply voltage and provide the first supply voltage to at least one of the plurality of devices; and a third backside pattern extending in the first direction along the first track between the first backside pattern and the second backside pattern, in the first backside wiring layer, wherein the third backside pattern is configured to receive a source supply voltage and provide the source supply voltage to a first device of the plurality of devices.