An integrated circuit device includes a substrate, a fin-type active area on the substrate, a nanosheet stacked structure including a plurality of nanosheets, a gate electrode surrounding the nanosheet stacked structure on the fin-type active area, and a source/drain region connected to one end of the plurality of nanosheets on the fin-type active area, wherein the source/drain region includes a first source/drain layer in contact with the upper surface of the fin-type active area and side surfaces of the plurality of nanosheets, a second source/drain layer covering the first source/drain layer, a third source/drain layer covering part of the second source/drain layer, and a fourth source/drain layer covering the second source/drain layer and the third source/drain layer.

Methods of manufacturing logic or memory devices are provided. The method includes selectively depositing a silicon-containing dielectric layer in a source/drain recess on a substrate and through an opening in an oxide liner within the source drain recess. The silicon-containing dielectric layer is then densified.

A device includes a stack of first nanostructures; a first insulating layer adjacent to the stack of first nanostructures; and a first source/drain region over the first insulating layer, wherein the first source/drain region includes: first semiconductor layers, wherein each first semiconductor layer covers a sidewall of a respective first nanostructure, wherein the first semiconductor layers includes a first semiconductor material; second semiconductor layers, wherein each second semiconductor layer covers a sidewall of a respective first semiconductor layer, wherein the second semiconductor layers includes a second semiconductor material different from the first semiconductor material; and a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer is a third semiconductor material different from the first semiconductor material and different from the second semiconductor material.

A semiconductor device includes a substrate including a fin-type active area and a device separation layer configured to cover both sidewalls of the fin-type active area, a pair of nanosheet stacks each including a lower nanosheet stack arranged on the fin-type active area and an upper nanosheet stack arranged on the lower nanosheet stack, an intermediate insulating layer arranged between the lower nanosheet stack and the upper nanosheet stack, a nanosheet separation wall arranged between each of the pair of nanosheet stacks and extending in a first horizontal direction, and a pair of gate lines extending on the pair of nanosheet stacks in a second horizontal direction, wherein the nanosheet separation wall separates respective lower nanosheet stacks in the pair of nanosheet stacks from each other in the second horizontal direction.

Exemplary semiconductor processing methods may include providing a first etchant precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A first layer of silicon-and-germanium-containing material, a second layer of silicon-and-germanium-containing material, and a layer of silicon-containing material may be disposed on the substrate. The methods may include providing a passivation precursor to the processing region. The methods may include contacting the substrate with the first etchant precursor and the passivation precursor. The contacting may selectively etch the first layer of silicon-and-germanium-containing material. The contacting may form a passivation material on the substrate.

The present inventive concept provides a method of manufacturing an oxide transistor, the method comprising: a step of forming a first channel layer by supplying a gas containing indium (In) and zinc (Zn) and supplying a gas containing oxygen; a step of forming a spacer on the first channel layer by supplying a gas containing gallium (Ga) and supplying a gas containing oxygen; and a step of forming a second channel layer on the spacer by supplying a gas containing indium (In) and zinc (Zn) and supplying a gas containing oxygen, and an oxide transistor made by the method.

A semiconductor device fabrication method may comprise: alternately and sequentially stacking a source/drain electrode layer forming a source/drain and a channel layer forming an oxide semiconductor channel; stacking a mask layer to surround a portion where a source/drain region is to be formed; exposing a channel layer of a channel region by etching and removing the source/drain electrode layer of the channel region exposed through the mask layer; and sequentially forming a gate dielectric layer and at least one gate electrode layer on the exposed channel layer of the channel region and on exposed lateral sides of the source/drain electrode layer of the source/drain region.

A semiconductor device, including: a lower interlayer insulating layer; an insulating pattern extending in a first horizontal direction on an upper surface of the lower interlayer insulating layer; a plurality of nanosheets on the insulating pattern and spaced apart in a vertical direction; an active cut including a first portion penetrating the lower interlayer insulating layer and the insulating pattern in the vertical direction, and a second portion separating the plurality of nanosheets in the first horizontal direction on an upper surface of the first portion, wherein a lower surface of the second portion is on an upper surface of the insulating pattern, and wherein the second portion is on inner sidewalls of the plurality of nanosheets in the first horizontal direction; a first source/drain region on a first side of the active cut on the insulating pattern, wherein the first source/drain region is on first outer sidewalls of the plurality of nanosheets; a second source/drain region on a second side of the active cut opposite to the first side of the active cut in the first horizontal direction on the insulating pattern, wherein the second source/drain region is on second outer sidewalls of the plurality of nanosheets; and a bottom source/drain contact penetrating the lower interlayer insulating layer and the insulating pattern in the vertical direction, wherein the bottom source/drain contact is electrically connected to the second source/drain region, and wherein the bottom source/drain contact overlaps the first portion of the active cut in the first horizontal direction, wherein a width of the upper surface of the first portion of the active cut in the first horizontal direction is smaller than a width of a lower surface of the first portion of the active cut in the first horizontal direction.

A semiconductor structure includes a substrate; a plurality of isolation stack layers located on the substrate, an isolation stack layer of the plurality of isolation stack layers including a plurality of isolation layers spaced apart in a vertical direction; and a plurality of channel layer structures each located on one isolation stack layer, a channel layer structure of the plurality of channel layer structures including a plurality of channel layers spaced apart in the vertical direction, sidewalls of adjacent channel layer structures forming a groove penetrating through the plurality of channel layer structures in the vertical direction, and the groove further extending into the plurality of isolation stack layers in the vertical direction.

Provided is a semiconductor device including a power distribution network layer on a lower surface of a substrate, a gate electrode on the substrate, a first source/drain pattern and a second source/drain pattern on the substrate, the first and second source/drain patterns each including a first pattern and a second pattern spaced apart from each other with the gate electrode therebetween, a through via structure penetrating the substrate and extending along a direction perpendicular to an upper surface of the substrate, the through via structure connecting the power distribution network layer and the first pattern of the first source/drain pattern, and a rear surface power via extending from below the second pattern of the first source/drain pattern to below the second pattern of the second source/drain pattern.