A semiconductor device may include an active pattern on a substrate, a first channel pattern and a second channel pattern provided on the active pattern and spaced apart from each other, a separation pattern between the first and second channel patterns, the separation pattern including a body portion and a head portion on the body portion, a gate electrode on the first and second channel patterns, and an inner insulating pattern on a side surface of the body portion. The inner insulating pattern may include a first portion between the first channel pattern and the separation pattern and between the second channel pattern and the separation pattern and a second portion between the gate electrode and the separation pattern. A width of the first portion may be larger than a width of the second portion.

An integrated circuit device includes a channel region, a gate line surrounding the channel region, a source/drain region contacting the channel region, and a backside via contact passing through a portion of the source/drain region in a vertical direction from a back side of the source/drain region. The source/drain region includes a bottom epitaxial layer protruding from a bottom surface of the source/drain region, a blocking epitaxial layer contacting the channel region and the bottom epitaxial layer, and a main epitaxial layer filling a space defined by the blocking epitaxial layer. A first dopant concentration of the bottom epitaxial layer is greater than a second dopant concentration of the blocking epitaxial layer and is greater than or equal to a third dopant concentration of the main epitaxial layer, and the backside via contact passes through at least a portion of the bottom epitaxial layer in the vertical direction.

A method of manufacturing an integrated circuit device includes sequentially forming a lower channel stack, an intermediate layer, and an upper channel stack on a substrate, forming a recess space by removing portions of the lower and upper channel stacks, and the intermediate layer, forming, sequentially, an insulating layer, a lower source/drain region and an upper source/drain region in the recess space, removing a sacrificial layer included in the lower and upper channel stacks and the intermediate layer, and forming a lower gate insulating layer on the lower channel stack and an upper gate insulating layer on the upper channel stack, forming a lower gate line on the lower gate insulating layer and an upper gate line on the upper gate insulating layer, and forming a gate isolation structure after the forming of the lower gate line and before the forming of the upper gate line.

A CFET transistor device, including: a substrate; a first semiconductor nanosheet and a second semiconductor nanosheet; an insulating layer arranged between the first and second nanosheets; a first gate arranged around a first part of the first nanosheet, and a second gate arranged around a first part of the second nanosheet; first inner spacers arranged against second parts of the first nanosheet, between which the first part of the first nanosheet is arranged, and second inner spacers arranged against second parts of the second nanosheet between which the first part is arranged; and wherein the first and second inner spacers respectively include first and second low-permittivity dielectric materials different from each other.

A semiconductor device includes a substrate, an active pattern on the substrate, a first channel pattern and a second channel pattern on the active pattern, a separation pattern between the first channel pattern and the second channel pattern, a gate electrode on the first channel pattern and the second channel pattern, and a gate insulating layer between the first channel pattern and the gate electrode and between the second channel pattern and the gate electrode, wherein the separation pattern includes a body portion and a head portion on the body portion, and the head portion includes an insulating pattern and an insulating layer on the insulating pattern.

The present disclosure provides a method of manufacturing a stacked nanosheet gate-all-around field-effect transistor and a field-effect transistor. The method includes: forming a stack on a substrate, the stack includes multiple nanosheet layers and multiple silicon alloy layers alternately stacked; etching each silicon alloy layer to form a first cavity, the first cavity is between two adjacent nanosheet layers; manufacturing a protective layer in the first cavity, the protective layer covers an inner surface of the first cavity and is recessed to form a second cavity; manufacturing a gate electrode and two source/drain electrodes based on the second cavity, an air spacer is between the gate electrode and any source/drain electrode; and removing a first dielectric constant medium in a first space, the first space is in the air spacer and surrounded by an upper surface of the uppermost nanosheet layer, the gate electrode and any source/drain electrode.

A gate-all-around transistor, comprising: a semiconductor substrate, where a fin-shaped protrusion is provided at a surface of the semiconductor substrate on one side; a source and a drain arranged on the top surface of the fin-shaped protrusion, respectively; a gate comprising a first gate part on the top surface of the fin-shaped protrusion between the source and the drain and a second gate part on a surface of the first gate part on the side away from the fin-shaped protrusion; a first dielectric layer on two opposite sides of the first gate part in a first direction; a second dielectric layer on two opposite sides of the second gate part in the first direction; where: the first direction is parallel to the direction of connecting the source and the drain; a dielectric constant of the first dielectric layer is greater than that of the second dielectric layer.

A semiconductor device includes a lower interlayer insulating layer, a first plurality of bottom nanosheets, a first plurality of upper nanosheets, an upper isolation layer between the first plurality of bottom nanosheets and the first plurality of upper nanosheets, a first bottom gate electrode on the lower interlayer insulating layer, a first upper gate electrode on an upper surface of the first bottom gate electrode, and a first active cut that extends into each of the first bottom gate electrode and the first plurality of bottom nanosheets in the vertical direction and is on an upper surface of the lower interlayer insulating layer, where the first active cut is spaced apart from the first upper gate electrode in the vertical direction, and where the first active cut at least partially overlaps each of the first upper gate electrode and the first plurality of upper nanosheets in the vertical direction.

A semiconductor device includes source and drain regions, a channel region between the source and drain regions, and a gate structure over the channel region. The gate structure includes a gate dielectric over the channel region, a work function metal layer over the gate dielectric and comprising iodine, and a fill metal over the work function metal layer.

A method of manufacturing a semiconductor device comprising: forming active structures; forming preliminary gate dielectric layers on the active structures; forming a first dipole layer including a first dipole material and a second dipole layer including a second dipole material on the preliminary gate dielectric layers; removing the first and second dipole layers in regions other than a first region of the active structures; removing a portion of the second dipole layer in regions other than a second region of the active structures, wherein each of the first and second regions includes at least two active structures, and the first region and the second region overlap to form an overlapping region; and performing a heat treatment process of diffusing the first and second dipole materials into the preliminary gate dielectric layers, wherein the overlapping region includes at least one of the active structures.