Semiconductor devices include stacked nanosheet channels with inner spacers between respective pairs of the stacked nanosheet channels. Dummy nanosheet remnants are below respective inner spacers, vertically aligned with the respective inner spacers. A source/drain structure is on sidewalls of the plurality of stacked nanosheet channels. A backside contact makes contact with the source/drain structure.

Provided is a semiconductor device including a lower source/drain pattern, a lower channel structure connected to the lower source/drain pattern, a lower gate electrode overlapping the lower channel structure and extending in a first direction, a lower active contact on the lower source/drain pattern, an upper channel structure overlapping the lower channel structure, an upper source/drain pattern connected to the upper channel structure, an upper gate electrode overlapping the upper channel structure and extending in the first direction, an interlayer structure between the lower channel structure and the upper channel structure, and a through active contact extending through the interlayer structure, and electrically connected to the upper source/drain pattern and the lower active contact.

A method includes alternately stacking a plurality of sacrificial layers and a plurality of channel layers on a first surface of a substrate; dividing the plurality of channel layers into a plurality of nanosheet stacks; forming a placeholder and a source/drain region on the placeholder between the plurality of nanosheet stacks; forming a first gate structure in an area from which the plurality of sacrificial layers have been removed; etching a portion of a second surface of the substrate to form an opening in the substrate and forming a backside insulating structure in the opening; etching the substrate so that at least a portion of the placeholder is exposed; removing the placeholder; and forming a liner on at least a portion of a side surface of the substrate from which the placeholder has been removed and forming a backside contact on the liner.

A method includes forming a multilayer stack, which includes a plurality of semiconductor nanostructures and a plurality of sacrificial layers. The plurality of semiconductor nanostructures and the plurality of sacrificial layers are located alternatingly. The method further includes laterally recessing the plurality of sacrificial layers to form lateral recesses, performing a doping process to dope a first dopant into the lateral recesses, forming inner spacers in the lateral recesses, performing an anneal process to diffuse the first dopant into the inner spacers, and forming a source/drain region contacting the inner spacers, wherein the source/drain region is electrically coupled to the plurality of semiconductor nanostructures.

A semiconductor device is provided. The semiconductor device includes: a first active pattern on a first active region of a substrate; a second active pattern on a second active region of the substrate, wherein the first active region is spaced apart from the second active region in a first direction; a first channel pattern that includes first semiconductor patterns that are spaced apart from each other and vertically stacked on the first active pattern; and a gate electrode on the first channel pattern. The gate electrode includes: first metal patterns on the first semiconductor patterns on the first active region; and a gap-fill pattern between the first metal patterns on the first active region. A maximum width in the first direction of the gap-fill pattern is less than a maximum width in the first direction of the first metal patterns.

A semiconductor device includes a substrate comprising a logic cell region and a peripheral region extending around the logic cell region, a logic device in the logic cell region and comprising a plurality of source/drain patterns, an upper active contact on and electrically connected to one of the source/drain patterns, a lower active contact below and electrically connected to another of the source/drain patterns, a conductive structure that penetrates the peripheral region of the substrate, a plurality of peripheral upper wiring lines in the peripheral region and connected to the conductive structure, and a plurality of peripheral lower wiring lines in the peripheral region and connected to the conductive structure opposite the peripheral upper wiring lines. A bottom surface of the conductive structure is lower than a bottom surface of the lower active contact, relative to a bottom surface of the substrate.

A semiconductor device may include a first gate electrode and a second gate electrode spaced apart from each other on a substrate, a first channel layer on one side of the first gate electrode, a second channel layer on one side of the second gate electrode, and a third gate electrode connecting the first gate electrode and the second gate electrode to each other. The first channel layer and the second channel layer may extend in a first direction and the first direction may be perpendicular to the substrate.

Provided are semiconductor devices and methods of fabricating the semiconductor device. The semiconductor device includes a channel, a first source/drain and a second source/drain being apart from each other in a first direction with the channel therebetween, a gate electrode surrounding the channel, an alternating-current wiring line configured to provide alternating current to the channel, and a first conductive contact connecting the alternating-current wiring line and the first source/drain to each other. A height difference from a first surface of the gate electrode facing the alternating-current wiring line to a first surface of the first source/drain in contact with the first conductive contact is less a height difference from a second surface of the gate electrode opposing the first surface of the gate electrode to a second surface of the first source/drain opposing the first surface of the first source/drain.

An integrated circuit device includes an active region extending lengthwise in a first direction on a substrate, a gate structure including a gate line, a high dielectric layer, and an interface dielectric layer, which extend lengthwise in a second direction perpendicular to the first horizontal direction on the active region, a nanosheet arranged on a fin upper surface of the active region and contacting the gate structure, a source/drain region arranged on the active region and contacting the nanosheet, and under the source/drain region in a direction perpendicular to both the first direction and the second direction, a lower insulating spacer arranged in a source/drain recess extending from the fin upper surface of the active region, wherein the interface dielectric layer includes a first portion extending on the nanosheet, and a second portion extending on the source/drain region, and wherein a first thickness of the first portion is different from a second thickness of the second portion.

The present disclosure discloses a gate-all-around field effect transistor which not only can suppress the occurrence of punch through in the substrates and direct leakage of current from the source region/drain region into the part under the channels, but also can facilitate heat release of the substrate, and minimizes the occurrence of device defects due to misalignment between the trench inner spacers and the device by forming trench inner spacers (TISs) and thus preventing source region/drain region impurities from diffusing into the substrate, and a method for manufacturing the same.