Provided are an oxide sintered compact whereby low carrier density and high carrier mobility are obtained when the oxide sintered compact is used to obtain an oxide semiconductor thin film by a sputtering method, and a sputtering target which uses the oxide sintered compact. This oxide sintered compact contains, as an oxide, one or more positive divalent elements selected from the group consisting of indium, gallium, nickel, cobalt, calcium, strontium, and lead. The gallium content is less than 0.08 to 0.20 in terms of Ga/(In+Ga) atomic ratio, and the positive dyad (M) content is 0.0001 to 0.05 in terms of M/(In+Ga+M) atomic ratio. In a crystalline oxide semiconductor thin film formed using the oxide sintered compact as a sputtering target, the carrier density is less than 110.sup.18 cm.sup.3, and the carrier mobility is at least 10 cm.sup.2V.sup.1sec.sup.1.

Provided is an oxide sintered body that, when used to obtain an oxide semiconductor thin film by sputtering, can achieve a low carrier concentration and a high carrier mobility. Also provided is a sputtering target using the oxide sintered body. The oxide sintered body contains, as oxides, indium, gallium, and at least one positive divalent element selected from the group consisting of nickel, cobalt, calcium, strontium, and lead. The gallium content, in terms of the atomic ratio Ga/(In+Ga), is from 0.20 to 0.45, and the positive divalent element content, in terms of the atomic ratio M/(In+Ga+M), is from 0.0001 to 0.05. The amorphous oxide semiconductor thin film, which is formed using the oxide sintered body as a sputtering target, can achieve a carrier concentration of less than 3.010.sup.18 cm.sup.3 and a carrier mobility of at least 10 cm.sup.2V.sup.1 sec.sup.1.

Technologies for a transistor with a ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a ferroelectric gate dielectric that is lattice matched to the channel of the transistor. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one transistor memory cell.

Technologies for a transistor with a ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a ferroelectric gate dielectric that is lattice matched to the channel of the transistor. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one transistor memory cell.