A power MOSFET and a sense MOSFET for detecting a current of the power MOSFET are formed in a semiconductor chip, and a source pad and a Kelvin pad are formed of a source electrode for the power MOSFET. The source pad is a pad for outputting the current flowing to the power MOSFET, and the Kelvin pad is a pad for detecting a source potential of the power MOSFET. The source electrode has a slit, and at least a part of the slit is arranged between the source pad and the Kelvin pad when seen in a plan view.

A semiconductor device includes a semiconductor layer. The entire length of an outer peripheral side among outer peripheral sides of a first gate electrode region and the entire length of an outer peripheral side among outer peripheral sides of a first resistance element region match a portion of an outer peripheral side, among outer peripheral sides of the semiconductor layer, that is orthogonal to a border line and has the shortest distance to a first gate pad. Among four corner portions of an outer periphery of the first gate electrode region, only one corner portion is included in the outer peripheral sides of the first resistance element region, the only one corner portion having the shortest distance to the border line and the shortest distance to an outer peripheral side, among the outer peripheral sides of the semiconductor layer, that is orthogonal to the border line.

A transistor component, in particular a trench power MISFET. The transistor component includes a substrate preferably made of silicon carbide, silicon, or gallium nitride, a source contact, a drain contact, and a trench structure with a gate.

The present application provides a high-voltage power semiconductor device and a method for manufacturing the same. A plurality of second resistive field plate structures is arranged in a terminal region of an epitaxial layer and extends through the epitaxial layer in a first direction to a substrate. The second resistive field plate structures are arranged concentrically and discontinuously around an active region in a first plane. The second resistive field plate structures and a third resistive field plate structure thereon form a -type combined resistive field plate structure.

A semiconductor chip includes a plurality of transistor cells arranged side by side along a first direction. The transistor cells include a gate interconnect that extends along a second direction orthogonal to the first direction, and a first semiconductor region that extends along the second direction and is of a first conductive type. The gate interconnect is arranged such that a mutual inductance generated between: the gate interconnect of one of the transistor cells; and the gate interconnect of another of the transistor cells is a negative value, the one and another transistor cells being next to each other. The first semiconductor region is arranged such that a mutual inductance generated between: the first semiconductor region of one of the transistor cells; and the first semiconductor region of another of the transistor cells is a negative value, the one and another transistor cells being next to each other.

A semiconductor device includes a semiconductor substrate having an element region and an outer peripheral region around the element region, and an upper electrode in contact with an upper surface the semiconductor substrate in the element region. The element region includes a p-type main region in contact with the upper electrode, and an n-type element drift region below the main region. The outer peripheral region includes a plurality of p-type guard rings disposed in multiple ring shapes surrounding the element region, a plurality of n-type spacing regions disposed between the guard rings, and an n-type outer drift region continuous with the element drift region and located below the guard rings and the spacing regions. At least one of the spacing regions is a high concentration spacing region having an n-type impurity concentration higher than that of the element drift region.

The present disclosure relates to a manufacturing method for a power semiconductor device (1, 40), comprising: forming multiple growth templates on a carrier substrate (2), comprising at least a first plurality of hollow growth templates (18) and a second plurality of hollow growth templates (28); selectively growing a first sequence of differently doped wide bandgap semiconductor materials in each one of the first hollow growth templates (18), thereby forming a corresponding plurality of first semiconductor structures (5) of a first type, in particular n+/p/n/n+ structures; and selectively growing a second sequence of differently doped wide bandgap semiconductor materials in each one of the second hollow growth templates (28), thereby forming a corresponding plurality of second semiconductor structures (6) of a second type, in particular n+/n/p/n+ structures. The disclosure further relates to a power semiconductor device (1, 40) comprising a carrier substrate (2), at least one dielectric layer (4, 27, 31), a plurality of first semiconductor structures (5) of a first type, and a plurality of second semiconductor structures (6) of a second type formed within the at least one dielectric layer (4, 27, 31).

The present application relates to a semiconductor device that includes: a device structure in a semiconductor body, with a first load terminal at a first side of the semiconductor body; a lower insulating layer on the first side of the semiconductor body; a conductor line in a lowermost metallization layer on the first side of the semiconductor body; and a load pad in an uppermost metallization layer on the first side of the semiconductor body. The uppermost metallization layer includes a copper layer and the lowermost metallization layer includes a tungsten layer. The conductor line is arranged in a trench in the lower insulating layer.

The present description provides a superjunction power semiconductor device. An example superjunction power semiconductor device has a die of semiconductor material comprising a structural layer with a first doping type having an active area where active cells are formed and an edge area surrounding the active area at the periphery of the die. An edge termination arrangement at the edge area has a plurality of edge-termination trenches extending through the structural layer filled with a dielectric material and having respective doped layers having a second doping type at sidewalls thereof. The edge termination arrangement has electrical connection structures, to electrically connect together the respective doped layers at the sidewalls of the edge-termination trenches.

Provided is a semiconductor device including a trench formed in a first main surface of a semiconductor chip, in which the trench has a portion extending in a first direction and a portion extending in a second direction different from the first direction in a continuous manner in plan view. The trench has a portion extending in a third direction different from the first direction and the second direction, in which the portion extending in the third direction is located between the portion extending in the first direction and the portion extending in the second direction in plan view, the portion extending in the first direction intersects the portion extending in the third direction at an obtuse angle, and the portion extending in the second direction intersects the portion extending in the third direction at an obtuse angle.