Provided is a wide band gap semiconductor device having high robustness against misalignment between gate electrodes (trenches) and a punch-through stopper layer. A technical concept is to configure the planar shape of the punch-through stopper layer from a pattern having periodicity in each of the X and Y directions constituting the plane, on the premise that the trenches extending in the Y direction out of the X direction and the Y direction constituting the plane are arranged at predetermined intervals in the X direction.

The present disclosure relates to a manufacturing method for a power semiconductor device (1, 40), comprising: forming multiple growth templates on a carrier substrate (2), comprising at least a first plurality of hollow growth templates (18) and a second plurality of hollow growth templates (28); selectively growing a first sequence of differently doped wide bandgap semiconductor materials in each one of the first hollow growth templates (18), thereby forming a corresponding plurality of first semiconductor structures (5) of a first type, in particular n+/p/n/n+ structures; and selectively growing a second sequence of differently doped wide bandgap semiconductor materials in each one of the second hollow growth templates (28), thereby forming a corresponding plurality of second semiconductor structures (6) of a second type, in particular n+/n/p/n+ structures. The disclosure further relates to a power semiconductor device (1, 40) comprising a carrier substrate (2), at least one dielectric layer (4, 27, 31), a plurality of first semiconductor structures (5) of a first type, and a plurality of second semiconductor structures (6) of a second type formed within the at least one dielectric layer (4, 27, 31).

A power semiconductor device includes: a semiconductor substrate; a power transistor formed in a cell field of the semiconductor substrate; a reference terminal; a sense terminal; and a depletion mode sense transistor integrated in the semiconductor substrate and having a voltage tap region of a first conductivity type. The voltage tap region is electrically connected to the sense terminal and follows a drift zone potential of the power transistor until a normally conducting channel of the depletion mode sense transistor pinches off. A pinch-off point of the normally conducting channel of the depletion mode sense transistor is designed such that a voltage between the sense terminal and the reference terminal is clamped below a maximum drain/collector voltage of the power semiconductor device.

According to one embodiment, a semiconductor device includes first and second electrodes, control electrodes between the first electrode and the second electrode, a semiconductor layer between the first electrode and the second electrode in ohmic contact with the first electrode, insulating portions between the semiconductor layer and each control electrode, third electrodes between control electrodes, each third electrode being sandwiched between adjacent insulating portions, and a second semiconductor region between adjacent third electrodes. The second semiconductor region being in Schottky contact with the third electrodes and having a width along the third direction that is greater than its width along the second direction.

A semiconductor device in an embodiment includes a plurality of first trenches which are recessed on one side in a thickness direction of a semiconductor substrate and have a first electrode accommodated therein. The semiconductor device includes a second trench which is recessed on the one side in the thickness direction and has a second electrode accommodated therein. When viewed from the thickness direction, the second trench surrounds each of the plurality of first trenches. The second trench includes a plurality of first extension portions which extend in a first direction which is orthogonal to the thickness direction and a plurality of second extension portions which extend in a second direction which is orthogonal to the thickness direction and intersects the first direction. A width of each of the plurality of second extension portions is narrower than a width of each of the plurality of first extension portions.

In an embodiment, a vertical transistor device includes a semiconductor substrate having a first major surface and a second major surface opposing the first major surface. At least one transistor cell formed in the semiconductor substrate includes a fin having an upper surface and side walls. The fin includes a source region, a body region and a drift zone that are located along a length of the fin. The body region extends between the source region and the drift zone. The transistor cell further includes a gate arranged on the upper surface and the side walls of the fin. A source pad is located on the first major surface and a drain pad is located on the second major surface of the semiconductor substrate.

The disclosure relates to a semiconductor die with a semiconductor body. The semiconductor die includes: a vertical transistor device with a first load region and a second load region at opposite sides of the semiconductor body; an additional transistor device with a source region at a first side of the semiconductor body, a gate trench, a body region aside the gate trench, and a drain region below the body region; an electrical isolation in the semiconductor body; and a vertical contact element extending from the first side into the semiconductor body. The electrical isolation is arranged laterally between the vertical transistor device and the additional transistor device. The vertical contact element makes electrical contact to the drain region of the additional transistor device and connects the drain region to the first side of the semiconductor body.

Described is a semiconductor die with a semiconductor body. The semiconductor die includes: a vertical transistor device; an additional transistor device having a channel region configured for a vertical current flow; an isolation trench extending into the semiconductor body; and an isolation well made of a second doping type. The isolation well is arranged vertically below the additional transistor device and arranged laterally between the additional transistor device and the vertical transistor device. The isolation trench extends to a depth which lies vertically between an upper end of the isolation well and the second side of the semiconductor body.

According to one embodiment, a semiconductor device includes first to third electrodes, a first conductive member, a semiconductor member, and a first insulating member. The first conductive member is electrically connected to the second electrode. The first conductive member includes a first conductive portion and a second conductive portion. A first material of the first conductive region of first conductive portion is different from a second material of the second conductive region of the second conductive portion. The semiconductor member is provided between the first electrode and the second electrode. The semiconductor member includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of the first conductivity type. The first semiconductor layer includes a first partial region and a second partial region.

An LDMOSFET is formed at a main surface of a semiconductor substrate. The LDMOSFET includes an n-type drain region, an n-type source region, an n-type drift region, a first p-type well region, and a second p-type well region, all formed in an n-type semiconductor layer. The n-type drift region is in contact with a bottom surface of the n-type drain region, the second p-type well region is in contact with a bottom surface of the n-type source region, and the first p-type well region is in contact with a bottom surface of the n-type drift region and a bottom surface of the second p-type well region. A p-type impurity concentration in the first p-type well region is lower than a p-type impurity concentration in the second p-type well region and is lower than an n-type impurity concentration in the n-type semiconductor layer.