H01L39/08

METHOD AND DEVICE FOR PROVIDING ANYONS, USE OF THE DEVICE

The present description relates to a method and a device for providing anyons that may be used for topological quantum computation. The method comprises the steps of providing a magnetic material containing at least one magnetic texture providing a superconductor containing at least one vortex; creating at least one magnetic texture-vortex pair by coupling the magnetic material to the superconductor, wherein each magnetic texture-vortex pair binds an anyon being localized at the vortex of the respective magnetic texture-vortex pair in the superconductor.

SUPERCONDUCTING GRAVITY GRADIOMETER AND SENSITIVITY IMPROVEMENT METHOD THEREOF

The invention discloses a superconducting gravity gradiometer and a sensitivity improvement method thereof including a pair of superconducting test masses, a pair of negative-stiffness superconducting coils, a pair of positive-stiffness superconducting coils, and a superconducting circuit coupling the test masses into two-degree-of-freedom superconducting magnetic spring oscillators. Superconducting wires are used to connect the negative-stiffness superconducting coils in series to form a superconducting loop, the differential mode stiffness of the two-degree-of-freedom superconducting magnetic spring oscillators is reduced, and the ratio of the common mode stiffness to the differential mode stiffness is increased. When using the method of the invention to configure the magnetic spring oscillator of a superconducting gravity gradiometer, when configuring a vertical diagonal component superconducting gravity gradiometer with a full magnetic suspension for the test mass, the sensitivity of gradient measurement is significantly improved.

Method related to tuning the performance of superconducting nanowire single photon detector via ion implantation

The present disclosure provides a method for making a single photon detector with a modified superconducting nanowire. The method includes: preparing a substrate; modifying a superconducting nanowire with stress on a surface of the substrate; and fabricating a superconducting nanowire single photon detector based on the superconducting nanowire with stress. Based on the above technical solution, in the superconducting nanowire single photon detector provided by the present disclosure, the device material layer film has a certain thickness, the critical temperature of the device material can be reduced, the uniformity of the device material and small superconducting transition width are ensured, thereby improving the detection efficiency of the device.

Superconductor ground plane patterning geometries that attract magnetic flux

Superconducting integrated circuit layouts are proofed against the detrimental effects of stray flux by designing and fabricating them to have one or more ground planes patterned in the x-y plane with a regular grid of low-aspect-ratio flux-trapping voids. The ground plane(s) can be globally patterned with such voids and thousands or more superconducting circuit devices and wires can thereafter be laid out so as not to intersect or come so close to the voids that the trapped flux would induce supercurrents in them, thus preventing undesirable coupling of flux into circuit elements. Sandwiching a wire layer between patterned ground planes permits wires to be laid out even closer to the voids. Voids of successively smaller maximum dimension can be concentrically stacked in pyramidal fashion in multiple ground plane layers having different superconductor transition temperatures, increasing the x-y area available for device placement and wire-up.

METHOD FOR FABRICATING AIR BRIDGE, AIR BRIDGE STRUCTURE, AND SUPERCONDUCTING QUANTUM CHIP

This disclosure includes a method for fabricating an air bridge, an air bridge structure, and a superconducting quantum chip, and relates to the field of circuit structures. In some examples, a method for fabricating an air bridge includes forming an air bridge brace structure on a substrate, and forming, on the air bridge brace structure and the substrate, an air bridge material layer with one or more openings in the air bridge material layer that reveal the air bridge brace structure. The air bridge material layer with the one or more openings is formed based on a patterned photoresist layer with patterns corresponding to the one or more openings. The method further includes removing, based on the one or more openings in the air bridge material layer, the air bridge brace structure to obtain the air bridge having the one or more openings.

Phononic devices and methods of manufacturing thereof

The present invention relates to a plurality of phononic devices and a method of manufacturing thereof. In one embodiment, highly sensitive superconducting cryogenic detectors integrate phononic crystals into their architecture. The phononic structures are designed to reduce the loss of athermal phonons, resulting in lower noise and higher sensitivity detectors. This fabrication process increases the qp generation recombination rate, thus, reducing the noise equivalent power (NEP) without sacrificing the scalability. A plurality of phononic devices, such as a kinetic inductance detector (KID), a transition edge sensor (TES) bolometer, and quarterwave backshort, can be manufactured according to the methods of the present invention.

Superconductivity device comprising a phononic crystal

The invention is directed to a device and method to engineer the superconducting transition width by suppressing the phonon populations responsible for the Cooper-pair decoherence below the superconducting transition temperature via phononic bandgap engineering. The device uses phononic crystals to engineer a phononic frequency gap that suppresses the decohering thermal phonon population just below the Cooper-frequency, and thus the normal conduction electron population. For example, such engineering can relax the cooling requirements for a variety of circuits yielding higher operational quality factors for superconducting electronics and interconnects.

SUPERCONDUCTING CIRCUIT PROVIDED ON AN ENCAPSULATED VACUUM CAVITY

Devices, systems, methods, and/or computer-implemented methods that can facilitate a qubit device comprising a superconducting circuit provided on an encapsulated vacuum cavity are provided. According to an embodiment, a device can comprise a substrate having an encapsulated vacuum cavity provided on the substrate. The device can further comprise a superconducting circuit provided on the encapsulated vacuum cavity.

SUPERCONDUCTING STRESS-ENGINEERED MICRO-FABRICATED SPRINGS
20220077376 · 2022-03-10 ·

A method of manufacturing superconductor structures includes depositing a release film on a substrate, forming a stack of films comprising an elastic material and a superconductor film, releasing a portion of the elastic material by selective removal of the release film so that portion lifts out of the substrate plane to form elastic springs. A method of manufacturing superconductor structures includes depositing a release film on a substrate, forming a stack of films comprising at least an elastic material, releasing a portion of the elastic material so that portion lifts out of a plane of the substrate to form elastic springs, and coating the elastic springs with a superconductor film.

REINFORCED THIN-FILM DEVICE
20210327712 · 2021-10-21 ·

A reinforced thin-film device (100, 200, 500) including a substrate (101) having a top surface for supporting an epilayer; a mask layer (103) patterned with a plurality of nanosize cavities (102, 102′) disposed on said substrate (101) to form a needle pad; a thin-film (105) of lattice-mismatched semiconductor disposed on said mask layer (103), wherein said thin-film (105) comprises a plurality of in parallel spaced semiconductor needles (104, 204) of said lattice-mismatched semiconductor embedded in said thin-film (105), wherein said plurality of semiconductor needles (104, 204) are substantially vertically disposed in the axial direction toward said substrate (101) in said plurality of nanosize cavities (102, 102′) of said mask layer (103), and where a lattice-mismatched semiconductor epilayer (106) is provided on said thin-film supported thereby.