H01L39/08

REDUCING PARASITIC CAPACITANCE AND COUPLING TO INDUCTIVE COUPLER MODES
20210384401 · 2021-12-09 ·

A qubit coupling device includes: a dielectric substrate including a trench; a first superconductor layer on a surface of the dielectric substrate where an edge of the first superconductor layer extends along a first direction and at least a portion of the superconductor layer is in contact with the surface of the dielectric substrate, and where the superconductor layer is formed from a superconductor material exhibiting superconductor properties at or below a corresponding critical temperature; a length of the trench within the dielectric substrate is adjacent to and extends along an edge of the first superconductor layer in the first direction, and where the electric permittivity of the trench is less than the electric permittivity of the dielectric substrate.

Superconducting quantum interference apparatus

This disclosure relates to Superconducting Quantum Interference Apparatuses, such as SQUID arrays and SQUIFs. A superconducting quantum interference apparatus comprises an array of loops each loop constituting a superconducting quantum interference device. The array comprises multiple columns, each of the columns comprises multiple rows connected in series, each of the multiple rows comprises a number of loops connected in parallel, and the number of loops connected in parallel in each row is more than two and less than 20 to improve a performance of the apparatus. It is an advantage that keeping the number of loops in parallel below 20 improves the performance of the apparatus. This is contrary to existing knowledge where it is commonly assumed that a larger number of parallel loops would increase performance.

SUPERCONDUCTING STRESS-ENGINEERED MICRO-FABRICATED SPRINGS
20210391525 · 2021-12-16 ·

A structure has a substrate, and a spring structure disposed on the substrate, the spring structure having an anchor portion disposed on the substrate, an elastic material having an intrinsic stress profile that biases a region of the elastic material to curl away from the substrate, and a superconductor film in electrical contact with a portion of the elastic material. A method of manufacturing superconductor structures includes depositing a release film on a substrate, forming a stack of films comprising an elastic material and a superconductor film, releasing a portion of the elastic material by selective removal of the release film so that portion lifts out of the substrate plane to form elastic springs. A method of manufacturing superconductor structures includes depositing a release film on a substrate, forming a stack of films comprising at least an elastic material, releasing a portion of the elastic material so that portion lifts out of a plane of the substrate to form elastic springs, and coating the elastic springs with a superconductor film.

Reducing parasitic capacitance and coupling to inductive coupler modes
11127892 · 2021-09-21 · ·

A qubit coupling device includes: a dielectric substrate including a trench; a first superconductor layer on a surface of the dielectric substrate where an edge of the first superconductor layer extends along a first direction and at least a portion of the superconductor layer is in contact with the surface of the dielectric substrate, and where the superconductor layer is formed from a superconductor material exhibiting superconductor properties at or below a corresponding critical temperature; a length of the trench within the dielectric substrate is adjacent to and extends along an edge of the first superconductor layer in the first direction, and where the electric permittivity of the trench is less than the electric permittivity of the dielectric substrate.

Method for the in situ production of Majorana material superconductor hybrid networks and to a hybrid structure which is produced using the method

A method for producing a hybrid structure, the hybrid structure including at least one structured Majorana material and at least one structured superconductive material arranged thereon includes producing, on a substrate, a first mask for structured application of the Majorana material and a further mask for structured growth of the at least one superconductive material, which are aligned relatively to one another, and applying the at least one structured superconductive material to the structured Majorana material with the aid of the further mask. The structured application of the Majorana material and of the at least one superconductive material takes place without interruption in an inert atmosphere.

SUPERCONDUCTING BUMP BOND ELECTRICAL CHARACTERIZATION

Test structures and methods for superconducting bump bond electrical characterization are used to verify the superconductivity of bump bonds that electrically connect two superconducting integrated circuit chips fabricated using a flip-chip process, and can also ascertain the self-inductance of bump bond(s) between chips. The structures and methods leverage a behavioral property of superconducting DC SQUIDs to modulate a critical current upon injection of magnetic flux in the SQUID loop, which behavior is not present when the SQUID is not superconducting, by including bump bond(s) within the loop, which loop is split among chips. The sensitivity of the bump bond superconductivity verification is therefore effectively perfect, independent of any multi-milliohm noise floor that may exist in measurement equipment.

Tapered connectors for superconductor circuits
11101215 · 2021-08-24 · ·

The various embodiments described herein include methods, devices, and circuits for reducing or minimizing current crowding effects in manufactured superconductors. In some embodiments, a superconducting circuit includes: (1) a first component having a first connection point, the first connection point having a first width; (2) a second component having a second connection point, the second connection point having a second width that is larger than the first width; and (3) a connector electrically connecting the first connection point and the second connection point, the connector including: (a) a first taper having a first slope and a non-linear shape; (b) a second taper having a second slope; and (c) a connecting portion connecting the first taper to the second taper, the connecting portion having a third slope that is less than the first slope and less than the second slope.

Majorana pair based qubits for fault tolerant quantum computing architecture using superconducting gold surface states

Under certain conditions, a fermion in a superconductor can separate in space into two parts known as Majorana zero modes, which are immune to decoherence from local noise sources and are attractive building blocks for quantum computers. Here we disclose a metal-based heterostructure platform to produce these Majorana zero modes which utilizes the surface states of certain metals in combination with a ferromagnetic insulator and a superconductor. This platform has the advantage of having a robust energy scale and the possibility of realizing complex circuit designs using lithographic methods. The Majorana zero modes are interrogated using planar tunnel junctions and electrostatic gates to selectively tunnel into designated pairs of Majorana zero modes. We give example of qubit designs and circuits that are particularly suitable for the metal-based heterostructures.

SINGLE PHOTON DETECTOR FOR REGULATING SUPERCONDUCTING NANO WIRE AND PREPARATION METHOD THEREFOR

The present disclosure provides a method for making a single photon detector with a modified superconducting nanowire. The method includes: preparing a substrate; modifying a superconducting nanowire with stress on a surface of the substrate; and fabricating a superconducting nanowire single photon detector based on the superconducting nanowire with stress. Based on the above technical solution, in the superconducting nanowire single photon detector provided by the present disclosure, the device material layer film has a certain thickness, the critical temperature of the device material can be reduced, the uniformity of the device material and small superconducting transition width are ensured, thereby improving the detection efficiency of the device.

MONOCRYSTALLINE THIN FILM, METHOD FOR MANUFACTURING SAME, AND PRODUCT USING SAME

Proposed are a thin film having single crystallinity and an excellent crystal orientation property, a method of manufacturing the same, and a semiconductor device, a battery device, a superconducting wire, and a superconducting article including the thin film having single crystallinity. The technical gist of the present disclosure includes a thin film having single crystallinity, which is formed by depositing a polycrystalline second material on an upper portion of a substrate including a polycrystalline first material and which has a crystal orientation property satisfying the following Relational Expression 1 at a grain boundary, a method of manufacturing the same, and a semiconductor device, a battery device, a superconducting wire, and a superconducting article including the thin film having single crystallinity.


0°<FWHM.sub.2≤3°  [Relational Expression 1] (FWHM.sub.2 is a full width at half maximum of a distribution curve of a misorientation angle at the grain boundary of the thin film).