A display apparatus can include a substrate, a pixel driving circuit on the substrate, and a light emitting device connected to the pixel driving circuit. The pixel driving circuit comprises a first thin film transistor, a second thin film transistor, and a third thin film transistor. The first thin film transistor comprises a first active layer and a first gate electrode. The second thin film transistor comprises a second active layer and a second gate electrode. The third thin film transistor comprises a third active layer and a third gate electrode, and the first active layer and the third active layer are disposed under the second active layer.

A thin film transistor unit comprises: a base substrate; a first lower thin film transistor and a second lower thin film transistor disposed on the base substrate and connected in parallel to each other; a first upper thin film transistor and a second upper thin film transistor disposed on the first lower thin film transistor and the second lower thin film transistor and connected in parallel to each other, wherein the first upper thin film transistor comprises a first upper active layer and a first upper gate electrode disposed on a first upper active layer, the second upper thin film transistor comprises a second upper active layer and a second upper gate electrode disposed on the second upper active layer, and the first upper gate electrode and the second upper gate electrode are electrically connected, with a first upper drain electrode being interposed therebetween.

An embodiment of the present disclosure provides a thin film transistor including an active layer, a gate insulating layer on the active layer, a gate electrode on the gate insulating layer, and a capping layer on the gate insulating layer, wherein the gate electrode and the capping layer are spaced apart from each other, wherein a part of the active layer overlaps the gate electrode, and wherein another part of the active layer overlaps the capping layer, and provides a method for manufacturing a thin film transistor and display device including the same.

The present disclosure provides a thin film transistor, a preparation method thereof, and a display panel. The thin film transistor includes an active layer and a first gate electrode located on a base substrate, the active layer includes a first film layer and a second film layer stacked on the base substrate, the second film layer is located between the first film layer and the first gate electrode, the first film layer includes oxygen element, the second film layer includes crystalline oxide, and the first film layer and the second film layer are formed via synchronous annealing. This approach not only prevents the thin film transistor channel from conducting due to insufficient oxygen content in the second film layer but also avoids issues such as etching residues caused by difficulties in etching the second film layer due to excessive oxygen content during the etching process.

A semiconductor device includes a channel including a two-dimensional semiconductor material, a source electrode and a drain electrode electrically connected to both ends of the channel, respectively, a two-dimensional material oxide layer on the channel, a dipole oxide layer on the two-dimensional material oxide layer, a dielectric layer on the dipole oxide layer, and a gate electrode on the dielectric layer.

A semiconductor device that can be reduced in size or highly integrated is provided. The semiconductor device includes first and second transistors and first to third conductors. The first transistor includes first and second gate electrodes between which a semiconductor layer of the first transistor is positioned. The second gate electrode is provided over the semiconductor layer of the first transistor to overlap the first gate electrode. The second transistor includes a third gate electrode over a semiconductor layer of the second transistor. The second transistor is stacked over the first transistor. The third gate electrode overlaps the second gate electrode. The first conductor electrically connects a source electrode of the first transistor and a source electrode of the second transistor. The second conductor electrically connects a drain electrode of the first transistor and a drain electrode of the second transistor. The third conductor electrically connects the first gate electrode, the second gate electrode, and the third gate electrode.

The present disclosure discloses a semiconductor device and a preparation method thereof. The preparation method includes: providing a semiconductor structure including a first insulating layer, a source layer on the first insulating layer, and a second insulating layer on the source layer; forming multiple drain portions embedded and arranged in an array on an upper portion of the second insulating layer; etching the second insulating layer by using multiple drain portions as masks until the source layer is exposed, to form multiple columnar bodies arranged in an array on an upper surface of the source layer, the columnar bodies including insulating columns on the source layer and drain portions on the insulating columns; forming a channel material layer surrounding the columnar bodies in a circumferential direction; and forming a gate dielectric layer and a gate structure on one side of the channel material layer away from the columnar bodies.

A capacitor with large capacitance, a transistor with excellent electrical characteristics, a transistor with high on-state current, or a transistor with small parasitic capacitance is provided. A device includes a first insulating layer, a first conductive layer over the first insulating layer, a second insulating layer over the first insulating layer and the first conductive layer, and a capacitor over the first conductive layer. The second insulating layer includes an opening portion that reaches the first conductive layer and includes a narrowed upper portion. A lower electrode, an upper electrode, and a dielectric of the capacitor each include a portion positioned in the opening portion. The lower electrode includes a portion in contact with the top surface of the first conductive layer and a portion provided along the opening portion.

The present disclosure provides a thin film transistor and a manufacturing method therefor, an array substrate, and a display panel. The thin film transistor includes a substrate and an active layer and a first gate electrode both located on the substrate. The active layer includes a first film layer and a second film layer stacked on the substrate, the second film layer is located between the first film layer and the first gate electrode, the first film layer and the second film layer are semiconductor film layers, the second film layer has a lower mobility than the first film layer, and the second film layer has a larger density than the first film layer.

A method of manufacturing a thin-film transistor in a display pixel circuit includes forming a gate electrode, forming, a gate insulating layer including a ferroelectric material on the gate electrode, forming a capping layer including a semiconductor layer on the gate insulating layer, and a metal layer on the semiconductor layer, wherein the semiconductor layer includes an oxide semiconductor, configuring the gate insulating layer to exhibit ferroelectricity, through a primary heat treatment process, and forming source/drain electrodes by patterning the metal layer.