H10F39/95

CHIP STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
20260026121 · 2026-01-22 ·

A chip structure including: a photonic integrated circuit (PIC) chip; an electronic integrated circuit (EIC) chip disposed on the PIC chip; and an optical block disposed on the PIC chip, spaced apart from the EIC chip in a horizontal direction, and configured to transfer optical signals to the PIC chip.

CHIP STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
20260026121 · 2026-01-22 ·

A chip structure including: a photonic integrated circuit (PIC) chip; an electronic integrated circuit (EIC) chip disposed on the PIC chip; and an optical block disposed on the PIC chip, spaced apart from the EIC chip in a horizontal direction, and configured to transfer optical signals to the PIC chip.

CHIP STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
20260029576 · 2026-01-29 ·

A chip structure includes a photonic integrated circuit chip including an optical coupler and a wave-guide extending in a first direction, an electronic integrated circuit chip on the photonic integrated circuit chip, a molding layer on the photonic integrated circuit chip, a first opening and a second opening in the molding layer, the second opening overlapping the first opening in a second direction perpendicular to the first direction, and a first dummy layer spaced apart from the electronic integrated circuit chip in the first direction and inside the first opening, wherein a first width in the first direction of the first opening is less than a second width in the first direction of the second opening.

CHIP STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
20260029576 · 2026-01-29 ·

A chip structure includes a photonic integrated circuit chip including an optical coupler and a wave-guide extending in a first direction, an electronic integrated circuit chip on the photonic integrated circuit chip, a molding layer on the photonic integrated circuit chip, a first opening and a second opening in the molding layer, the second opening overlapping the first opening in a second direction perpendicular to the first direction, and a first dummy layer spaced apart from the electronic integrated circuit chip in the first direction and inside the first opening, wherein a first width in the first direction of the first opening is less than a second width in the first direction of the second opening.

SEMICONDUCTOR PACKAGES AND SEMICONDUCTOR DEVICES COMPRISING HEAT TRANSFER MEMBER
20260052987 · 2026-02-19 ·

Provided is a semiconductor package that may improve heat dissipation performance, including a package substrate on a system substrate, in which the package substrate includes a first surface and a second surface opposite the first surface, the second surface facing the system substrate, a connection member electrically connecting the system substrate and the package substrate, a first semiconductor chip on the first surface of the package substrate, a second semiconductor chip on the second surface of the package substrate, and electrically connected to the first semiconductor chip, and a heat transfer member between the second semiconductor chip and the system substrate.

SEMICONDUCTOR PACKAGES AND SEMICONDUCTOR DEVICES COMPRISING HEAT TRANSFER MEMBER
20260052987 · 2026-02-19 ·

Provided is a semiconductor package that may improve heat dissipation performance, including a package substrate on a system substrate, in which the package substrate includes a first surface and a second surface opposite the first surface, the second surface facing the system substrate, a connection member electrically connecting the system substrate and the package substrate, a first semiconductor chip on the first surface of the package substrate, a second semiconductor chip on the second surface of the package substrate, and electrically connected to the first semiconductor chip, and a heat transfer member between the second semiconductor chip and the system substrate.

DEVICE COMPRISING AN EXPOSED CONDUCTIVE LAYER AND A METHOD OF FABRICATING THE DEVICE

An electronic system includes a first device and a second device bonded to the first device. The first device includes: a semiconductor substrate with an opening; a stack having metal layers and conductive vias; and a conductive layer including aluminum having a first face in contact with the stack and a second face, opposite the first face, that is partially exposed through the opening. The metal layers and the conductive vias of the stack are made of a conductive material different from aluminum.

PHOTODETECTOR COMPRISING COUPLED FABRY-PEROT RESONATORS

A photodetector incorporates Fabry-Perot resonators that are coupled in order to concentrate radiation to be detected in a photoconductive material. It is then possible to use photoconductive nanocrystals that are deposited from a colloidal solution of the nanocrystals, while at the same time having a high photodetection sensitivity. It is thereby possible to form a matrix-array of such photodetectors on an image sensor readout circuit, while avoiding having to join a separate detection circuit to the readout circuit using intermediate solder balls. Additionally, each photodetector may be produced easily using deposition and selective removal processes, and may be able to be reconfigured so as to have variable detection sensitivity spectra.

PHOTODETECTOR COMPRISING COUPLED FABRY-PEROT RESONATORS

A photodetector incorporates Fabry-Perot resonators that are coupled in order to concentrate radiation to be detected in a photoconductive material. It is then possible to use photoconductive nanocrystals that are deposited from a colloidal solution of the nanocrystals, while at the same time having a high photodetection sensitivity. It is thereby possible to form a matrix-array of such photodetectors on an image sensor readout circuit, while avoiding having to join a separate detection circuit to the readout circuit using intermediate solder balls. Additionally, each photodetector may be produced easily using deposition and selective removal processes, and may be able to be reconfigured so as to have variable detection sensitivity spectra.

IMAGE SENSOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
20260101603 · 2026-04-09 ·

A semiconductor package may include a package substrate, a first image sensor chip and a second image sensor chip, which are on the package substrate and are spaced apart from each other in a first direction, and a bonding wire connecting the first image sensor chip to the second image sensor chip. The first image sensor chip may include a first conductive pad, and the second image sensor chip may include a second conductive pad. The bonding wire may be connected to the first conductive pad and the second conductive pad.