A display panel includes a substrate, electronic elements, first electrodes, and connection lines. The substrate includes a first main surface and a second main surface, and multiple side surfaces connecting the two main surfaces. At least one side surface is a selected side surface. Each connection line includes a first line segment, a second line segment and a third line segment. The third line segment is disposed on the second main surface, and includes a bonding portion and a non-binding portion, the bonding portion being farther away from the selected side surface relative to the non-binding portion. A maximum dimension of the bonding portion in a direction perpendicular to an extension direction thereof is less than a maximum dimension of the non-bonding portion in a direction perpendicular to an extension direction thereof. Bonding portions of third line segments are used for bonding a circuit board.

Embodiments of the present disclosure provide a thin film transistor (TFT) back panel a light-emitting diode (LED) display panel and a manufacturing method therefor. In the TFT back panel provided in the embodiments of the present disclosure, a pressure-sensitive transistor is disposed. When a first pressure-sensitive material layer is subjected to a pressure, a pressure-sensitive transistor is turned on to generate a current, and a pressure signal is converted into an electrical signal. Changes in a pressure applied to the TFT back panel during transfer and pressing of an LED can be monitored in real time by monitoring a magnitude of the electrical signal.

In an embodiment an optoelectronic component includes a plurality of active regions configured to produce electromagnetic radiation, wherein the active regions are laterally arranged next to each other and spaced from each other, wherein the plurality of active regions comprises at least one first-type active region and at least one second-type active region, which are based on the same semiconductor material system and have different bandgaps in order to produce different electromagnetic radiations, wherein the first-type active region is laterally surrounded by a first-type mask and the second-type active region is laterally surrounded by a second-type mask, wherein the masks are of different materials, and wherein the materials of the masks are selected from SiO.sub.2, SiN, TiO, TiN, or Al.sub.2O.sub.3.

In an embodiment a method includes providing a carrier, applying a plurality of semiconductor chips to the carrier, the semiconductor chips being spaced apart from one another such that cavities are formed between the semiconductor chips, introducing a photo-exposable material, at least the cavities being filled with the photo-exposable material, exposing the photo-exposable material, wherein parts of the photo-exposable material, which are downstream of the semiconductor chips with respect to an exposure remain unexposed, removing unexposed parts of the photo-exposable material, wherein recesses are formed, applying a functional layer to the semiconductor chips, and removing the exposed photo-exposable material.

An adapter device for chip packaging test is disclosed in the present disclosure. The adapter device for chip packaging test includes: a connection plate comprising a plurality of packaging testing units. Each packaging testing unit includes: a plate slot for accommodating a micro chip, a signal transmission sheet coupled with the plate slot, a signal connector coupled with the plate slot, and a chip substrate. In some embodiments, the adapter device for chip packaging test further includes: an adapter plate coupled with the connection plate through an inter-plate connection region included in the adapter plate. A method for chip packaging testing includes bonding a plurality of the micro chips to the chip substrates of the connection plate, coupling the connection plate with the adapter plate, inspecting the plurality of micro chips, and identifying a faulty micro chip using the identification code.

In some embodiments, methods for fabricating micro-LEDs may include bonding a semiconductor wafer to a Complementary Metal-Oxide-Semiconductor (CMOS) wafer via one or more adhesive layers, etching the LED epilayer and the one or more adhesive layers to form a plurality of micro-LED structures, and fabricating an electrode layer on the plurality of micro-LED structures. The semiconductor wafer may include an LED epilayer including an n-GaN layer, a p-GaN layer, and an active layer positioned between the n-GaN layer and the p-GaN layer. Prior to the bonding of the semiconductor layer to the CMOS wafer, a stress release pattern may be formed in the LED epilayer. The stress release pattern may include a plurality of geometrical shapes (e.g., squares, rectangles, hexagons, rings, etc.) that may facilitate the release of mechanical stresses induced during the subsequent processing of the semiconductor wafer and/or the fabrication of the micro-LEDs.

In an embodiment an optoelectronic arrangement includes a carrier, at least one optoelectronic device configured to emit light through at least one emission surface and including at least one side edge and a center with a rotational axis substantially perpendicular to the at least one emission surface, and a breakable anchoring structure coupling the at least one optoelectronic device to the carrier on a surface facing away the at least one emission surface and including a first main surface that is at least partially attached to the at least one optoelectronic device, wherein the first main surface is displaced with respect to the center and includes a corner facing the center with a smallest distance to it, and wherein the first main surface comprises a triangular shape with an angle at the corner of less than 60 or wherein the first main surface comprises a non-rectangular shape that is symmetrical along an axis through the corner and the center.

A display device includes a substrate having a light emitting area and a non-light emitting area. A light emitting element us disposed in the light emitting area on the substrate. A light transmission layer is disposed on the light emitting element. The light transmission layer includes a plurality of openings spaced apart from each other. The light transmission layer includes a plasma-treated surface part. A plurality of light control patterns is disposed in the plurality of openings.

The invention relates to a method for manufacturing an optoelectronic device (1) with a diode array (20), including the following steps: producing an electret layer (30) having conversion zones (Zc) separated two-by-two by a spacing zone (Ze) with zero surface potential, where each conversion zone (Zc) is formed of a plurality of so-called polarized elementary zones (32) with non-zero surface potential, spaced apart two-by-two by a so-called non-polarized elementary zone (33) with zero surface potential, such that the conversion zone (Zc) has a structured surface potential; producing color conversion pads (P), by placing the electret layer (30) in contact with a colloidal solution(S) containing photoluminescent particles (p).

An optoelectronic device, comprising a stack including a plurality of light-emitting diodes disposed at a distance from one another, and a plurality of electrically conductive terminals arranged between the diodes, and a light confinement layer extending over the stack and comprising reflective walls defining between them, spaces located to the right of each diode. Further, the confinement layer includes the porous alumina in at least one of the spaces, the porous alumina having, in at least one space, preferably in at least two of the spaces, even in each space, from among the at least some spaces, at least two open pores on a first face of the confinement layer which is located opposite the stack. The optical crosstalk phenomena are advantageously reduced.