Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a substrate, a first semiconductor layer over the substrate, a second semiconductor layer over the first semiconductor layer and including a channel region sandwiched between a first source/drain region and a second source/drain region, a first plurality of nanostructures disposed over the channel region, a first leakage block layer over the first source/drain region, a second leakage block layer over the second source/drain region, a dielectric layer on the first leakage block layer, a first source/drain feature on the dielectric layer and in contact with first sidewalls of the first plurality of nanostructures, and a second source/drain feature disposed on the second leakage block layer and in contact with second sidewalls of the first plurality of nanostructures. The first leakage block layer and the second leakage block layer includes an undoped semiconductor material.

In an embodiment, an exemplary method includes forming a source/drain opening extending into a substrate, forming a semiconductor layer in a bottom portion of the source/drain opening, forming a dielectric feature in the source/drain opening and on the semiconductor layer, epitaxially growing a source/drain feature in the source/drain opening, wherein the source/drain feature is in direct contact with the dielectric feature, removing the semiconductor layer and a portion of the substrate disposed directly under the semiconductor layer to form a trench, selectively removing the dielectric feature to enlarge the trench, after the selectively removing of the dielectric feature, forming a silicide layer in the enlarged trench, and depositing a conductive layer in the enlarged trench and in direct contact with the silicide layer.

The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a fin-shape base protruding from a semiconductor substrate. A top surface of the semiconductor substrate is in a (100) crystal plane, and a top surface of the fin-shape base is in a (110) crystal plane. The semiconductor device also includes channel members disposed over the top surface of the fin-shape base, a gate structure wrapping around at least one of channel members, a gate spacer extending along a sidewall of the gate structure, a source/drain feature abutting the channel members, and a dopant-free epitaxial feature under the source/drain feature. A top surface of the source/drain feature is in a (110) crystal plane. A top surface of the dopant-free epitaxial feature is in a (110) crystal plane.

A method of forming a semiconductor device includes: forming a gate structure over a fin; forming an interlayer dielectric (ILD) layer over the fin around the gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure on opposing sides of the fin, where the first and second dielectric plugs cut the gate structure into a plurality of discrete segments; forming a patterned mask layer over the ILD layer, where an opening of the patterned mask layer exposes a segment of the gate structure interposed between the first and second dielectric plugs; etching, using the patterned mask layer as an etching mask, the segment of the gate structure using an isotropic etching process to form a recess in the gate structure; extending the recess into the fin by performing an anisotropic etching process; and after extending the recess, filling the recess with a dielectric material.

A semiconductor device includes insulating isolation patterns each including a void, semiconductor patterns respectively stacked on the insulating isolation patterns, gate structures respectively extending around the semiconductor patterns, first and second source/drain patterns respectively connected to opposing sides of the plurality of semiconductor patterns in a first direction, an active contact structure extending between insulating isolation patterns adjacent to the first source/drain pattern and connected to the first source/drain pattern, a dummy contact structure extending between the insulating isolation patterns adjacent to the second source/drain pattern and electrically isolated from the second source/drain pattern, and an interconnection line on lower surfaces of the insulating isolation patterns, electrically connected to the active contact structure, and electrically isolated from the dummy contact structure.

Provided is a semiconductor device and method of manufacturing same, the semiconductor device including: a plurality of active patterns on a substrate; a source/drain pattern on the substrate; a power rail in the substrate; a pillar pattern between the plurality of active patterns; a channel pattern on the pillar pattern; a backside conductive contact between the source/drain pattern and the power rail; and a liner pattern on the pillar pattern, wherein the liner pattern includes: a first portion that covers a top surface of a lower portion of the backside conductive contact; and a second portion that extends from the first portion and along a sidewall of the lower portion of the backside conductive contact.

A semiconductor circuit structure includes a semiconductor substrate with an original semiconductor surface, an active region within the semiconductor substrate, and a transistor formed based on the active region. The transistor includes a gate structure, a first spacer neighboring to a first sidewall of the gate structure, and a second spacer neighboring to a second sidewall of the gate structure. Wherein a thermal conductivity of the first spacer or the second spacer includes is higher than the thermal conductivity of silicon nitride (Si.sub.3N.sub.4).

A semiconductor device includes a substrate, and an interconnection layer on the substrate. The interconnection layer includes an interconnection structure having a first interconnection line therein that includes a metal alloy containing a single phase of ruthenium and a non-ruthenium first element having a concentration in a range from greater than 0 at % to 40 at % in the metal alloy. In the event the first element is molybdenum, the concentration of the first element in the metal alloy may range from 0.1 at % to 30 at %; but, in the event the first element is tungsten, the concentration of the first element in the metal alloy may range from 0.1 at % to 40 at %.

A semiconductor device may include a channel pattern on a substrate, a source/drain pattern electrically connected to the channel pattern, a gate electrode on the channel pattern, an interlayer insulating layer on the source/drain pattern, and an active contact that extends into the interlayer insulating layer and is electrically connected to the source/drain pattern. The active contact may include a lower active contact, which includes a barrier pattern and a lower metal pattern on the barrier pattern, and an upper active contact on the lower active contact. The upper active contact may include an upper metal pattern and an insulating pattern on side surfaces of the upper metal pattern. The lower metal pattern and the upper metal pattern may be in contact with each other.

Provided is a semiconductor device including a first active pattern and a second active pattern on a substrate, a first source/drain pattern and a first channel pattern on the first active pattern, a second source/drain pattern and a second channel pattern on the second active pattern, and a gate electrode crossing each of the first channel pattern and the second channel pattern. Along a horizontal extension direction of the gate electrode, a first width of an upper surface of the first channel pattern is greater than a second width of an upper surface of the second channel pattern, and an upper surface of the first source/drain pattern is located at a vertically higher level than the upper surface of the first channel pattern.