A semiconductor device including a first fin pattern and a second fin pattern, a first source/drain pattern overlapping the first fin pattern, a second source/drain pattern overlapping the second fin pattern, a lower separation dielectric layer between the first and second fin patterns and between the first and second source/drain patterns, a cover dielectric layer on the first source/drain pattern and the second source/drain pattern, and an upper separation dielectric layer overlapping the lower separation dielectric layer may be provided. A lower portion of the upper separation dielectric layer may be between the first source/drain pattern and the second source/drain pattern. An upper portion of the upper separation dielectric layer may be at a level higher than a level of the cover dielectric layer.

A semiconductor device includes a plurality of first gate structures arranged along a first direction and extending in a second direction, at least one first gate structure of the plurality of first gate structures corresponding to a first transistor region; a plurality of second gate structures arranged along the first direction and aligned with ones of the first gate structures in the second direction, at least one second gate structure of the plurality of second gate structures corresponding to a second transistor region; an insulating structure extending in the second direction and separating the plurality of first gate structures from the plurality of second gate structures; and a first conductive via in the insulating structure and configured to carry a signal for the first transistor region.

Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and a first channel layer and a second channel layer. The semiconductor structure further includes an isolation structure over the substrate and a first gate structure over the first channel layer and the isolation structure. The semiconductor structure further includes a second gate structure over the second channel layer and the isolation structure and an isolation feature laterally sandwiched between the first gate structure and the second gate structure and extending over the isolation structure. In addition, the isolation feature has a top width and a bottom width that is greater than the top width, and an interface between the isolation feature and the first gate structure includes a curved profile.

A semiconductor device includes a substrate having a front surface and a rear surface. The device includes a first transistor disposed on the front surface of the substrate and including a first gate electrode and first source/drain patterns disposed adjacent to the first gate electrode. The device includes a front surface dummy stack structure disposed on the first transistor and electrically floated, the front surface dummy stack structure extending from a lower end to an upper end, the lower end being spaced apart from the first transistor. The front surface dummy stack structure includes alternately stacked front surface dummy vias front surface dummy wires that overlap the first gate electrode such that heat generated in the first transistor is transferred to the upper end of the front surface dummy stack structure through the plurality of front surface dummy vias and the plurality of front surface dummy wires.