A semiconductor structure comprises a first nanosheet device having at least one first channel layer and a first gate, a second nanosheet device disposed above the first nanosheet device and having at least one second channel layer and a second gate, and an isolation layer disposed between the first nanosheet device and the second nanosheet device to electrically isolate the first nanosheet device and the second nanosheet device.

A method includes forming a multilayer stack, which includes a plurality of semiconductor nanostructures and a plurality of sacrificial layers. The plurality of semiconductor nanostructures and the plurality of sacrificial layers are located alternatingly. The method further includes laterally recessing the plurality of sacrificial layers to form lateral recesses, performing a doping process to dope a first dopant into the lateral recesses, forming inner spacers in the lateral recesses, performing an anneal process to diffuse the first dopant into the inner spacers, and forming a source/drain region contacting the inner spacers, wherein the source/drain region is electrically coupled to the plurality of semiconductor nanostructures.

Various embodiments of the present disclosure provide a method for forming a semiconductor device structure. In one embodiment, the method includes forming a fin over a substrate, wherein the fin comprises first semiconductor layers and second semiconductor layers alternating stacked. The method also includes forming a sacrificial gate structure over the fin, removing portions of the fin not covered by the sacrificial gate structure, replacing the second semiconductor layers with a sacrificial dielectric material, recessing edge portions of the sacrificial dielectric material to form cavities between the first semiconductor layers, forming a dielectric spacer in the cavities by depositing a conformal layer of a dielectric liner layer on exposed surfaces of each cavity, forming source/drain features on opposite sides of the sacrificial gate structure, and replacing the sacrificial gate structure and the sacrificial dielectric material with a gate structure wrapping around the first semiconductor layers.

A semiconductor device structure and methods of forming the same are described. The method includes forming a fin structure over a substrate and depositing one or more spacers on a portion of the fin structure. The one or more spacers are deposited on sidewalls of the fin structure. The method further includes removing a first portion of the one or more spacers to expose the fin structure and recessing the fin structure. A first byproduct layer is formed on a second portion of the one or more spacers. The method further includes passivating the first byproduct layer, softening the first byproduct layer, removing a portion of the first byproduct layer to expose the recessed fin structure, and further recessing the fin structure.

A semiconductor structure is provided. The semiconductor structure includes channel members disposed above a substrate, a gate structure wrapping around the channel members, inner spacers adjacent to the gate structure, and a source/drain feature abutting the channel members. One of the inner spacers includes a middle dielectric portion and a shield dielectric portion that covers surfaces of the middle dielectric portion. The dielectric constant of the shield dielectric portion is greater than the dielectric constant of the middle dielectric portion.

A semiconductor device may include: a lower insulating pattern including a first surface, a second surface opposite to the first surface in a first direction, and a sidewall connecting the first surface to the second surface; a first sheet pattern in contact with the first surface of the lower insulating pattern; a second sheet pattern on the first sheet pattern, spaced apart from the first sheet pattern in the first direction; a gate structure including an inner gate structure, the inner gate structure being between the first sheet pattern and the second sheet pattern, extending in a second direction, and including a gate electrode and a gate insulating film; a source/drain pattern connected to the first sheet pattern and the second sheet pattern; and a bottom insulating spacer below the source/drain pattern in the first direction, and overlapped with the source/drain pattern in the first direction.

A semiconductor device may include a gate structure, a plurality of channel patterns spaced apart from each other in a first direction, each of the plurality of channel patterns extending through the gate structure in a second direction substantially perpendicular to the first direction, a source/drain layer adjacent to the gate structure in the second direction, the source/drain layer contacting the plurality of channel patterns, a first spacer on a sidewall of the gate structure in the second direction and including an insulating material, and a second spacer on a sidewall of the first spacer in the second direction, the second spacer contacting the source/drain layer. The first spacer may include opposite edge portions in the first direction and a center portion in the first direction, and a width of the first spacer in the second direction may increase from the opposite edge portions toward the center portion.