A method for manufacturing a semiconductor structure includes forming a plurality of semiconductor stack portions spaced apart from each other by a plurality of recesses, each of which includes two sacrificial layer portions and a channel layer portion disposed therebetween, in which the channel layer portion has a plurality of crystal planes and is formed with a first straight lateral surface which is aligned with one of the crystal planes that has a lowest etching rate for an etchant to be used for laterally etching the channel layer portion among those of the crystal planes of the channel layer portion which are able to expose to the recesses; and laterally etching the channel layer portion using the etchant to permit the channel layer portion to be formed with a second straight lateral surface.

A method for manufacturing a split double gate transistor includes: forming a first fin on a substrate; removing sacrificial layers from a portion of the first fin; sequentially forming a first gate insulating layer, a channel layer and a protection layer on exposed portions of each gate metal layer; performing a patterning process to form a second fin; patterning the second fin to form a plurality of first recesses and a plurality of second recesses; forming a plurality of inner spacer layers; forming a first gate component, a drain component and a source component; removing the protection layer; and sequentially forming a second gate insulating layer, a plurality of gate connectors, and a second gate component.

A transistor and a method for fabricating the transistor are provided. The semiconductor structure transistor includes a base, a low-dimensional material layer, a plurality of spacers, a source, a drain, and a gate stack. The low-dimensional material layer is provided above the base. The plurality of spacers is provided on a surface of the low-dimensional material layer away from the base and spaced apart from each other. The source and the drain are provided on the surface of the low-dimensional material layer away from the base, respectively. The gate stack is provided on the surface of the low-dimensional material layer away from the base and between the source and the drain, in which the gate stack, the source and the drain are separated by the spacers, and in contact with the spacers, respectively. Therefore, the transistor has advantages of excellent comprehensive performance, high process compatibility, and good device uniformity.

A semiconductor structure is provided. The semiconductor structure includes channel members disposed above a substrate, a gate structure wrapping around the channel members, inner spacers adjacent to the gate structure, and a source/drain feature abutting the channel members. One of the inner spacers includes a middle dielectric portion and a shield dielectric portion that covers surfaces of the middle dielectric portion. The dielectric constant of the shield dielectric portion is greater than the dielectric constant of the middle dielectric portion.

A method for forming a semiconductor structure is provided. The method includes alternately stacking channel layers and sacrificial layers on a substrate in a vertical direction to form a semiconductor stack, patterning the semiconductor stack to form a fin-shaped structure protruding from the substrate, forming a source/drain trench in the fin-shaped structure, laterally recessing the sacrificial layers in the fin-shaped structure to form first recesses, and enlarging the first recesses to form second recesses. One of the second recesses has a vertical dimension greater than a thickness of the sacrificial layer after enlarging the first recesses. The method further includes forming inner spacers in the second recesses, and forming a source/drain feature in the source/drain trench.

A semiconductor device may include a gate structure, a plurality of channel patterns spaced apart from each other in a first direction, each of the plurality of channel patterns extending through the gate structure in a second direction substantially perpendicular to the first direction, a source/drain layer adjacent to the gate structure in the second direction, the source/drain layer contacting the plurality of channel patterns, a first spacer on a sidewall of the gate structure in the second direction and including an insulating material, and a second spacer on a sidewall of the first spacer in the second direction, the second spacer contacting the source/drain layer. The first spacer may include opposite edge portions in the first direction and a center portion in the first direction, and a width of the first spacer in the second direction may increase from the opposite edge portions toward the center portion.