A method including: providing a design data of an integrated circuit (IC), the design data comprising a first cell; identifying a first conductive line in the first cell as a critical internal net of the first cell, wherein the first conductive line is electrically connected between an input terminal of the first cell and an output terminal of the first cell; providing a library of the first cell, wherein the library includes a table of timing or power parameters of the first cell based on a multidimensional input set associated with the critical internal net; updating the design data by determining a timing or power value of the first cell based on the table; performing a timing analysis on the updated design data; and forming a photomask based on the updated design data.

An example is a non-transitory computer-readable storage medium including stored instructions. The instruction, which when executed by one or more processors, cause the one or more processors to: obtain a representation of a design under test (DUT) and split the representation of the DUT into multiple partitions. The representation of the DUT includes optimizable leaf instances and timing paths between respective timing startpoints and timing endpoints. Splitting the representation of the DUT into multiple partitions is based on respective slacks of the timing endpoints. Each partition of the multiple partitions includes one or more timing endpoints of the timing endpoints and a transitive fan-in including one or more optimizable leaf instances along one or more timing paths of the timing paths that terminate at the respective one or more timing endpoints.

A method includes obtaining, by a computer processor according to computer instructions, data models of intellectual property (IP) cores for hierarchical clock domain crossing (CDC) and reset domain crossing (RDC) verification, where the IP cores include reusable units of logic for a system on a chip (SoC), and performing, by the computer processor based on the data models of the IP cores, the hierarchical CDC and RDC verification for the SoC according to integration of the IP cores in the SoC, where the hierarchical CDC and RDC verification includes consistency verification of functional assumptions with structural analysis of the IP cores individually and in a context of use in the SoC.

An improved system for monitoring clock duty cycles, comprising: a first monitoring circuit configured to record a first quantity of high levels of the monitored clock signal sampled by a first random clock signal; a second monitoring circuit configured to record a second quantity of high levels of the monitored clock signal sampled by a second random clock signal, wherein the phase of the second random clock is adjusted by a second adjustment degree based on a first clock; a third monitoring circuit configured to record a third quantity of high levels of the monitored clock signal sampled by a third random clock signal, wherein the phase of the third random clock is the reverse of that of the first random clock; and a calculation module configured to determine a duty cycle of the monitored clock based on the first quantity, the second quantity, and the third quantity.

A computer implemented method for a multi-layer integrated circuit routing tool connecting sources with nets to sinks in a hierarchical multi-layer integrated circuit design environment, the method including creating a cycle reach table containing a first set of information parameters for two dimensional nets per metal layer combination, creating a repeater reach table containing a second set of information parameters per constraint class, preparing a working list of nets, preparing a list of blocks larger than repeater reach dimensions, connecting a source pin to a sink pin on preassigned metal layers, by routing the net based on the given constraint class.

A semiconductor device includes a first circuit element, a layer of dielectric material, a first wire and a second wire in the layer of dielectric material, and an array of wires in the layer of dielectric material, wherein a first wire at a first track in the array of wires is electrically connected to the first circuit element, the first wire having a first width, a second wire at a second track in the array of wires has a second width different from the first width, and a third track in the array of wires between the first track and the second track is an empty track, and wherein the first wire is asymmetric with respect to the first track in the array of wires.

To facilitate crosstalk analysis for an IC design, a plurality of input vectors are input into a gate-level simulation. In response, the gate-level simulation determines timing windows for all nets within the IC design, may perform aggressor pruning, and may then determine and output aggressor/victim pairs and associated features for the IC design. This gate-level simulation may be accelerated utilizing one or more graphics processor units (GPUs). Additionally, the aggressor/victim pairs and associated features for the IC design are then input into a trained machine learning environment, which outputs predicted delta delays for each of the aggressor/victim pairs. In this way, crosstalk analysis may be performed more accurately and efficiently.

Disclosed are a chip power consumption analyzer and an analyzation method thereof. The analyzation method includes the following. Design information of a circuit is received. A plurality of clock arriving times of a plurality of circuit cells in the circuit are calculated based on the design information, and a base cell type is set among a plurality of cell types according to the clock arriving times. Base demand current information of the base cell type is established, and a plurality of demand current information of the circuit cells is obtained. A plurality of demand peak currents of a plurality of bump current sources are predicted according to the demand current information and a plurality of position information of the circuit cells.

A clock design method for two or more physical partition structures based on a same system clock. The method includes determining a distance of each circuit logic from the system clock; based on the distance between each circuit logic and the system clock, obtaining a plurality of clock nodes from the system clock to cause a delay of each clock node compared to the system clock to change with the distance from each circuit logic and the system clock, the greater the distance, the greater the delay; connecting each circuit logic to a corresponding clock node based on size of each circuit logic and the distance; and converging timing of each circuit logic by adjusting the delay of each clock node compared to the system clock.

This invention is related to an integrated circuit optimization system and method wherein an edge-triggered sequential element such as a flip-flop is transformed into an equivalent module including level-sensitive latches of multiple phases, subsequently level-sensitive latch-based optimization techniques are applied such as level-sensitive latch retiming and better-than-worst-case design such as based on prediction and detection of signal propagation in a path through a level-sensitive latch, resulting in an integrated circuit including separate level-sensitive latches of multiple phases, edge-triggered sequential elements, and combinational logic networks.