A semiconductor device includes a first semiconductor element, a plurality of leads, a plurality of wires and a sealing resin covering the first semiconductor element, the plurality of wires, and at least a part of each of the plurality of leads. The plurality of leads include a first lead. The plurality of wires include a plurality of first wires each having a first bonding portion connected to the first semiconductor element and a second bonding portion connected to the first lead. The first lead includes a first portion extending in an x first direction. The second bonding portions of the plurality of first wires are connected to the first portion and arranged in a plurality of rows along the x direction.

A power module having a first integrated power board having a first positive terminal, a first power semiconductor die, a first middle point terminal, a second power semiconductor die and a first negative terminal, a second integrated power board having a second positive terminal, another first power semiconductor die, a second middle point terminal, another second power semiconductor die and a second negative terminal, a PCB busbar having opposite first face and second face and having power conductive tracks and connection pads, on both said first face and said second face, wherein said first integrated power board has its first positive terminal, first middle point terminal and first negative terminal connected to connection pads on said first face, wherein said second integrated power board has its first positive terminal, first middle point terminal and first negative terminal connected to further connection pads on said second face.

A semiconductor power device is described, having: a package; a power die arranged within the package and integrating a power structure that generates a load electric current designed to be supplied to an electric load. The device is also provided, within the package, with: at least a first conductive path designed to be flown through by a first sensing current, which is a function of the load electric current; and a current sensor with magnetic-based operation, integrated into a sensor die coupled to the first conductive path and which generates a current sensing signal on the basis of the first sensing current and indicative of the load electric current.

A semiconductor device includes a plurality of transistors electrically connected in parallel to each other, each of the plurality of transistors including a first pad; and a conductive member. The first pad is a source pad or an emitter pad. The first pad includes a first connection region; and a second connection region and a third connection region, the first connection region being located between the second connection region and the third connection region. The semiconductor device includes a first connection member that connects the first connection region to the conductive member; a second connection member that connects second connection regions of two transistors among the plurality of transistors; and a third connection member that connects third connection regions of the two transistors among the plurality of transistors.

A semiconductor device includes a conductive plate, and a terminal including a bonding portion having a rectangular plate shape in a plan view and having a bottom surface bonded to the conductive plate and a top surface having an indentation area with indentations, and a ramp portion integrally connected to the bonding portion at a rear end thereof and extending from the bonding portion upward in a direction away from the top surface. The indentation area includes a plurality of sub-indentation areas each having a thickness from the bottom surface in a thickness direction orthogonal to the bottom surface is less than a thickness of the bonding portion from the bottom surface to the top surface at an area other than the indentation area.

An inverter device includes: an interconnect substrate having a first interconnect layer and a second interconnect layer; and a plurality of transistors arranged in a middle layer, each having a source region and a drain region surrounding the source region on one face. The plurality of transistors include a first transistor placed with the one face facing the first interconnect layer and having a drain connected to a first interconnect in the first interconnect layer and a source connected to a second interconnect in the first interconnect layer. The first interconnect overlaps the drain region of the first transistor in planar view, and the second interconnect extends from the opening of the first interconnect to the position overlapping the source region of the first transistor in planar view.

A semiconductor module includes first to fourth semiconductor elements, a plurality of wiring patterns, a first power source terminal, second power source terminals, a first intermediate point terminal and a second intermediate point terminal, and a full bridge circuit is formed in the semiconductor module. The semiconductor module further includes a temperature detection element; first and second temperature detection wiring patterns; and first and second temperature detection terminals. The temperature detection element is disposed in a region surrounded by a first switching path and a second switching path. The semiconductor module is configured to reduce noises caused by a parasitic capacitance between a second wiring pattern and a first temperature detection wiring pattern, and a parasitic capacitance between a fourth wiring pattern and a first temperature detection wiring pattern.

A semiconductor device includes: a base plate; semiconductor elements; and wiring elements disposed adjacent to the respective semiconductor elements on the base plate. A diode sensing a temperature of an adjacent one of the semiconductor elements is disposed in each of the wiring elements. The wire pad of each of the wiring elements is disposed to face the wire pad of the adjacent semiconductor element. The diode of each of the wiring elements is disposed closer to the adjacent semiconductor element. The wire pad of each of the semiconductor elements is connected through a wire to the wire pad of the wiring element adjacent to the semiconductor element.

A package and method is disclosed. In one example, the package includes a carrier comprising a component mounting area from which a lateral extension extends, the lateral extension being configured for being clamped by an encapsulant tool pin during encapsulation, an electronic component mounted on the component mounting area, and an encapsulant encapsulating at least part of the electronic component and part of the carrier. The lateral extension is laterally retracted with respect to a neighboring vertical sidewall of the encapsulant. The encapsulant laterally covers the lateral extension.

An embodiment includes a method for floorplanning of a circuit region of an IC device which includes: obtaining a floorplan for the circuit region; determining a location of an in-die stitching boundary for the floorplan, the in-die stitching boundary extending in a first direction across the floorplan; placing one or more rows of filler cells in an in-die stitching sub-region of the floorplan, wherein the one or more rows of filler cells extend in the first direction and the in-die stitching sub-region extends along the in-die stitching boundary; and placing in each of a first and a second sub-region of the floorplan on opposite sides of the in-die stitching sub-region, circuit cells in a plurality of rows extending in parallel in the first direction, wherein the filler cells have a critical dimension which is greater than a corresponding critical dimension of the circuit cells of the first and second sub-regions.